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publication number s29gl_128s_01gs_00 revision 02 issue date march 21, 2011 gl-s mirrorbit ? eclipse ? flash non-volatile memory family gl-s mirrorbit ? family cover sheet s29gl01gs 1 gbit (128 mbyte) s29gl512s 512 mbit (64 mbyte) s29gl256s 256 mbit (32 mbyte) s29gl128s 128 mbit (16 mbyte) cmos 3.0 volt core with versatile i/o ? data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s29gl_128s_01gs_00 revision 02 issue date march 21, 2011 general description the spansion ? s29gl01g/512/256/128s are mirrorbit eclipse flash pr oducts fabricated on 65 nm process technology. these devices offer a fast page access time as fast as 15 ns with a co rresponding random access time as fast as 90 ns. they feature a write buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. this makes these devices ideal for today?s embedded applications that require higher density, better per formance and lower power consumption. distinctive characteristics ? 65 nm mirrorbit technology ? single supply (v cc ) for read / program / erase (2.7v to 3.6v) ? versatile i/o ? feature ? wide i/o voltage range (v io ): 1.65v to v cc ? x16 data bus ? asynchronous 32-byte page read ? 512-byte programming buffer ? programming in page multiples, up to a maximum of 512-bytes ? single word and multiple program on same word options ? sector erase ? uniform 128-kbyte sectors ? suspend and resume commands for program and erase operations ? status register, data polling, and ready/busy pin methods to determine device status ? advanced sector protection (asp) ? volatile and non-volatile protection methods for each sector ? separate 1024-byte one time program (otp) array with two lockable regions ? common flash interface (cfi) parameter table ? industrial temperature range (-40c to +85c) ? 100,000 erase cycles for any sector typical ? 20-year data retention typical ? packaging options ? 56-pin tsop ? 64-ball lae fortified bga, 9 mm x 9 mm gl-s mirrorbit ? eclipse ? flash non-volatile memory family s29gl01gs 1 gbit (128 mbyte) s29gl512s 512 mbit (64 mbyte) s29gl256s 256 mbit (32 mbyte) s29gl128s 128 mbit (16 mbyte) cmos 3.0 volt core with versatile i/o ? data sheet (preliminary)
4 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) performance summary maximum read access times density voltage range random access time (t acc ) page access time (t pac c ) ce# access time (t ce ) oe# access time (t oe ) 128 mb full v cc = v io 90 15 90 25 versatileio v io 1002510035 256 mb full v cc = v io 90 15 90 25 versatileio v io 1002510035 512 mb full v cc = v io 1001510025 versatileio v io 1102511035 1 gb full v cc = v io 1001510025 versatileio v io 1102511035 typical program and erase rates buffer programming (512 bytes) 1.2 mb/s sector erase (128 kbytes) 655 kb/s maximum current consumption active read at 5 mhz, 30 pf 60 ma program 100 ma erase 100 ma standby 100 a
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 5 data sheet (preliminary) table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 software interface 2. address space maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 flash memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 device id and cfi (id-cfi) aso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 2.3 status register aso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 data polling status aso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 secure silicon region aso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 sector protection control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 device protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 command protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 secure silicon region (otp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 sector protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. embedded operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 embedded algorithm controller (eac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 program and erase summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 status monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5 error types and clearing procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.6 embedded algorithm performance table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6. software interface reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 device id and common flash interface (id-cfi) aso ma p . . . . . . . . . . . . . . . . . . . . . . . . . 56 hardware interface 7. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 7.1 address and data configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2 input/output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3 versatile i/o feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.4 ready/busy# (ry/by#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.5 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8. signal protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.1 interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.2 power-off with hardware data protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3 power conservation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.4 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.5 write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2 latchup characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.5 capacitance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10. timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.1 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.2 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 10.3 power-on reset (por) and warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11. physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.1 56-pin tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.2 64-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13. other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.1 links to software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.2 links to application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.3 specification bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.4 contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 7 data sheet (preliminary) figures figure 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3.1 advanced sector protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5.1 word program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5.2 write buffer programming operation with data pol ling status . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5.3 write buffer programming operat ion with status register . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5.4 sector erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5.5 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 5.6 toggle bit program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 9.2 power-down and voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 9.3 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 9.4 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 figure 10.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 10.2 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 10.3 power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 10.4 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 10.5 back to back read (tacc) operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 10.6 back to back read operation (trc)timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 10.7 page read timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 10.8 back to back write operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 10.9 write to read (tacc) operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 10.10 write to read (tce) operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 figure 10.11 read to write (ce# vil) operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 10.12 read to write (ce# toggle) operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 10.13 program operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10.14 chip/sector erase operation timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10.15 data# polling timing diagram (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10.16 toggle bit timing diagram (during embedded algorith ms) . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10.17 dq2 vs. dq6 relationship diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10.18 back to back (ce#) write operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 10.19 (ce#) write to read operation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 11.1 56-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 11.2 56-pin thin small outline package (tsop), 14 x 20 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 11.3 64-ball fortified ball grid array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 11.4 lae064?64-ball fortified ball grid array (fbga), 9 x 9 mm . . . . . . . . . . . . . . . . . . . . . . . . 87
8 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) tables table 1.1 s29gl-s address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.1 s29gl01gs sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2.2 s29gl512s sector and memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2.3 s29gl256s sector and memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2.4 s29gl128s sector and memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2.5 id-cfi address map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2.6 secure silicon region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.1 sector protection states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3.2 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5.1 write buffer programming command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.2 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.3 data polling status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.4 embedded algorithm characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.5 read command state transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.6 read unlock command state transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 5.7 erase state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.8 erase suspend state command transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.9 erase suspend unlock state command transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.10 erase suspend - dyb state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.11 erase suspend - program command state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.12 erase suspend - program suspend command state transistion. . . . . . . . . . . . . . . . . . . . . 47 table 5.13 program state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.14 program unlock state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.15 program suspend state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.16 lock register state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.17 cfi state command transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.18 secure silicon sector state command transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.19 secure silicon sector unlock state command transiti on. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.20 secure silicon sector progra m state command transition . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 5.21 password protection command state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 5.22 non-volatile protection comma nd state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5.23 ppb lock bit command stat e transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5.24 volatile sector protection command state transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5.25 state transition definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.1 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.2 id (autoselect) address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.3 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.4 cfi system interface string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.5 cfi device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.6 cfi primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 7.1 i/o summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 8.1 interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 9.2 power-up/power-down voltage and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 9.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 9.4 connector capacitance for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 9.5 connector capacitance for tsop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 10.1 test specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 10.2 power on and reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 10.3 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 10.4 read operation v io = v cc = 2.7v to 3.6v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 10.5 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 10.6 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 10.7 alternate ce# controlled write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 9 data sheet (preliminary) 1. product overview the gl-s family consists of 128-mbit to 1gbit, 3.0v core, versatile i/o, non-vola tile, flash memory devices. these devices have a 16-bit (word) wide data bus and use only word boundary addresses. all read accesses provide 16 bits of data on each bus transfer cycle. all writes take 16 bits of data from each bus transfer cycle. figure 1.1 block diagram : note: ** a max gl01gs = a25, a max gl512s = a24, a max gl256s = a23, a max gl128s = a22 the gl-s family combines the best features of execute in place (xip) and data storage flash memories. this family has the fast random a ccess of xip flash along with the high density and fast program speed of data storage flash. read access to any random location takes 90 ns to 120 ns depending on device density and i/o power supply voltage. each random (initial) access reads an entire 32-byte aligned group of data called a page. other words within the same page may be read by cha nging only the low order 4 bits of word address. each access within the same page takes 15 ns to 30 ns. this is called page mode read. changing any of the higher word address bits will select a different page and begin a new initial access. all read accesses are asynchronous. inp u t/o u tp u t b u ffer s x-decoder y-decoder chip en ab le o u tp u t en ab le logic er as e volt a ge gener a tor pgm volt a ge gener a tor timer v cc detector s t a te control comm a nd regi s ter v cc v ss v io we# wp# ce# oe# s tb s tb dq15 ? dq0 s ector s witche s ry/by# re s et# d a t a l a tch y-g a ting cell m a trix addre ss l a tch a m a x **?a0
10 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) the device control logic is subdivided into two parallel operating sections, the host interface controller (hic) and the embedded algorithm controller (eac). hic monito rs signal levels on the device inputs and drives outputs as needed to complete read and write data tr ansfers with the host system. hic delivers data from the currently entered address map on read transfers; places write transfer address and data information into the eac command memory; notifies the eac of power transition, hardware reset, and write transfers. the eac looks in the command memory, after a write transfer, for legal command sequences and performs the related embedded algorithms. changing the non-volatile data in the memory arra y requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the device internal eac. the main algorithms perform programming and erase of the main array data. the host system writes command codes to the flash device address spac e. the eac receives the commands , performs all the necessary steps to complete the command, and provides status information during the progress of an ea. the erased state of each memory bit is a logic 1. pr ogramming changes a logic 1 (high) to a logic 0 (low). only an erase operation is able to change a 0 to a 1. an erase operation must be performed on an entire 128-kbyte aligned and length group of data call a sector. when shipped from spansion all sectors are erased. programming is done via a 512-byte write buffer. it is possible to write from 1 to 256 words, anywhere within the write buffer before starting a programming operat ion. within the flash memory array, each 512-byte aligned group of 512 bytes is called a line. a programmi ng operation transfers vola tile data from the write buffer to a non-volatile memory array line. t he operation is called write buffer programming. the write buffer is filled with 1?s after reset or th e completion of any operation using the write buffer. any locations not written to a 0 by a write to buffer command are by default still filled with 1?s. any 1?s in the write buffer do not affect data in the memory array during a programming operation. as each page of data that was loaded into the writ e buffer is transferred to a memory array line. sectors may be individually protected from program an d erase operations by the ad vanced sector protection (asp) feature set. asp provides several, hardware a nd software controlled, vo latile and non-volatile, methods to select which sectors are prot ected from program and erase operations. note that in future technology nodes the data poll ing status feature will not be supported. the user is strongly advised to use the status register to determine device status. table 1.1 s29gl-s address map type count addresses address within page 16 a3 - a0 address within write buffer 256 a7 - a0 page 4096 a15 - a4 write-buffer-line 256 a15 - a8 sector 1024 (1 gb) 512 (512 mb) 256 (256 mb) 128 (128 mb) amax - a16
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 11 data sheet (preliminary) software interface 2. address space maps there are several separate address spaces that may appear within the address range of the flash memory device. one address space is visible (entered) at any given time. ? flash memory array: the main non-volatile memory ar ray used for storage of data that may be randomly accessed by asynchronous read operations. ? id/cfi: a flash memory array used for spansion fact ory programmed device characteristics information. this area contains the device identification (id) and common flash interface (cfi) information tables. ? secure silicon region (ssr): a one time programmable (otp) non-volatile memory array used for spansion factory programmed permanent data, and customer programmable permanent data. ? lock register: an otp non-volatile word used to configure the asp features and lock the ssr. ? persistent protection bits (ppb): a non-volatile flas h memory array with one bit for each sector. when programmed, each bit protects the relate d sector from erasure and programming. ? ppb lock: a volatile register bit used to enable or disable prog ramming and erase of the ppb bits. ? password: an otp non-volatile array used to store a 64-bit password used to enable changing the state of the ppb lock bit when using password mode sector protection. ? dynamic protection bits (dyb): a volatile array with one bit for each sector. when set, each bit protects the related sector from erasure and programming. ? status register: a volatile register used to display embedded algorithm status. ? data polling status: a volatile register used as an al ternate, legacy software compatible, way to display embedded algorithm status. the main flash memory array is the primary and default address space but, it may be overlaid by one other address space, at any one time. each alternate addr ess space is called an address space overlay (aso). each aso replaces (overlays) the entire flash devic e address range. any address range not defined by a particular aso address map, is reserved for future use. all read accesses outsid e of an aso address map returns non-valid (undefined) data. the locations will disp lay actively driven data but the meaning of whatever 1?s or 0?s appear are not defined. there are four address map modes that determine what appears in the flash device address space at any given time: ? read mode ? data polling mode ? status register (sr) mode ? address space overlay (aso) mode in read mode the entire flash memory array may be directly read by the host system memory controller. the memory device embedded algorithm controller (eac), put s the device in read mode during power-on, after a hardware reset, after a command reset, or after an embedded algorithm (ea) is suspended. read accesses and commands are accepted in read mode. a subset of commands are accepted in read mode when an ea is suspended. while in any mode, the status regi ster read command may be issued to cause the status register aso to appear at every word address in the device address spac e. in this status regi ster aso mode, the device interface waits for a read access and, any write a ccess is ignored. the next read access to the device accesses the content of the status register, exits the status regi ster aso, and returns to the previous (calling) mode in which the status register read command was received. in ea mode the eac is performing an embedded algorith m, such as programming or erasing a non-volatile memory array. while in ea mode, none of the main flas h memory array is readable because the entire flash device address space is replaced by the data polling st atus aso. data polling st atus will appear at every word location in the device address space.
12 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) while in ea mode, only the program / erase suspend command or the status register read command will be accepted. all other commands are ignored. thus, no other aso may be entered from the ea mode. when an embedded algorithm is suspended, the data polling aso is visible until the device has suspended the ea. when the ea is suspended the data polling aso is exited and flash array data is available. the data polling aso is reentered when the suspended ea is resumed, until the ea is again suspended or finished. when an embedded algorithm is completed, t he data polling aso is exited and the device goes to the previous (calling) mode (from whic h the embedded algorithm was started). in aso mode, one of the remaining overlay address sp aces is entered (overlaid on the main flash array address map). only one aso may be entered at any one time. commands to the device affect the currently entered aso. only certain commands are valid for each aso. these are listed in the table 6.1 on page 54 , in each aso related section of the table. the following asos have non-volatile data that may be programmed to change 1?s to 0?s: ? secure silicon region ? lock register ? persistent protection bits (ppb) ? password ? only the ppb aso has non-volat ile data that may be erased to change 0?s to 1?s when a program or erase command is issued while o ne of the non-volatile asos is entered, the ea operates on the aso. the aso is not readable while the ea is active. when the ea is completed the aso remains entered and is again readable. suspend and resume commands are ignored during an ea operating on any of these asos. 2.1 flash memory array the s29gl-s family has uniform sector arch itecture with a sector size of 128 kb. table 2.1 to table 2.4 shows the sector architectu re of the four devices. table 2.1 s29gl01gs sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 1024 sa00 0000000h-000ffffh sector starting address ::? sa1023 3ff0000h-3ffffffh sector ending address table 2.2 s29gl512s sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 512 sa00 0000000h-000ffffh sector starting address ::? sa511 1ff0000h-1ffffffh sector ending address table 2.3 s29gl256s sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 256 sa00 0000000h-000ffffh sector starting address ::? sa255 0ff0000h-0ffffffh sector ending address
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 13 data sheet (preliminary) note: these tables have been condensed to show sector related information for an entire device on a single page sectors and their address ranges that are not ex plicitly listed (such as sa001-sa510) have sectors starting and ending addresses that form the same pattern as all other sectors of t hat size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh. 2.2 device id and cfi (id-cfi) aso there are two tr aditional methods fo r systems to identify the type of fl ash memory installed in the system. one has traditionally been called autoselect and is now referred to as device identification (id). the other method is called common flash interface (cfi). for id, a command is used to enable an address space overlay where up to 16 word locations can be read to get jedec manufacturer identification (id), device id, and some configuration and protection status information from the flash memory . the system can use the manufacture r and device ids to select the appropriate driver software to use with the flash device. cfi also uses a command to enable an address spac e overlay where an extendable table of standard information about how the flash memory is organized and operates can be read. with this method the driver software does not have to be written with the specifics of each possible memory device in mind. instead the driver software is written in a more general way to handle many different devi ces but adjusts the driver behavior based on the information in the cfi table. traditionally these two address spaces have used separate commands and were separate overlays. however, the mapping of these two address spaces ar e non-overlapping and so can be combined in to a single address space and appear together in a single over lay. either of the traditional commands used to access (enter) the autoselect (id) or cfi overlay wi ll cause the now combined id-cfi address map to appear. the id-cfi address map appears within, and overlays th e flash array data of, the sector selected by the address used in the id-cfi enter comm and. while the id-cfi aso is entered the content of all other sectors is undefined. the id-cfi address map starts at location 0 of th e selected sector. locations above the maximum defined address of the id-cfi aso to the maximum address of the selected sector have undefined data. the id-cfi enter commands use the same address and data values used on previous generation memories to access the jedec manufacturer id (autoselect) and common flash interface (cfi) in formation, respectively. for the complete address map see table 6.2 on page 57 . 2.2.1 device id the joint electron device engineering council (jedec ) standard jep106t defines the manufacturer id for a compliant memory. common industry usage defined a method and format for reading the manufacturer id and a device specific id from a memory device. t he manufacturer and device id information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm. spansion has added additional fields within this 32-byte address space. table 2.4 s29gl128s sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 128 sa00 0000000h-000ffffh sector starting address ::? sa127 07f0000h-07fffffh sector ending address table 2.5 id-cfi address map overview word address description read / write (sa) + 0000h to 000fh device id (traditional autoselect values) read only (sa) + 0010h to 0079h cfi data structure read only (sa) + 0080h to ffffh undefined read only
14 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) the original industry format was structured to work with any memory data bus width e. g. x8, x16, x32. the id code values are traditionally byte wide but are lo cated at bus width address boundaries such that incrementing the device address inputs will read successive byte, word, or double word locations with the id codes always located in the least significant byte loca tion of the data bus. because the device data bus is word wide each code byte is located in the lower half of each word location. the original industry format made the high order byte always 0. spansion has modified the format to use both bytes in some words of the address space. for the detail description of the device id address map see table 6.2 on page 57 . 2.2.2 common flash memory interface the jedec common flash interface (c fi) specification (jesd68 .01) defines a standard ized data structure that may be read from a flash memory device, which allows vendor-specified soft ware algorithms to be used for entire families of devices. the data structure contains information for system configuration such as various electrical and timing parameters, and special function s supported by the device. software support can then be device-independent, device id-independent, and fo rward-and-backward-compatible for entire flash device families. the system can read cfi informat ion at the addresses within the selected sector as shown in device id and common flash interface (id-cfi) aso map on page 56 . like the device id information, cfi information is struct ured to work with any memory data bus width e. g. x8, x16, x32. the code values are always byte wide but are located at data bus width address boundaries such that incrementing the device address reads successive byte, word, or double word locations with the codes always located in the least significant byte location of the data bus. because the data bus is word wide each code byte is located in the lower half of each word location and the high order byte is always 0. for further information, please refer to the spansion cfi specification, version 1.4 (or later), and the jedec publications jep137-a and jesd68.01 . please contact jedec ( http://www.jedec.org/ ) for their standards and the spansion cfi specification ma y be found at the spansion web site ( http://www.spansion.com/su pport/technicaldocuments/pages/applicationnotes.aspx at the time of this document's publication) or by contacting a local spansion sales office listed on the web site. 2.3 status register aso the status register aso cont ains a single word of registered volat ile status for embedded algorithms. when the status register read command is issued, the current status is captured by t he register and the aso is entered. the status register content ap pears at all word locations in the device address space. however, it is recommended to read the status only at word location 0 for future compatibility. the first read access in the status register aso exits the aso and returns to t he address space map in use when the status register read command was issued. 2.4 data polling status aso the data polling status aso contains a single word of vo latile memory indicating the progress of an ea. the data polling status aso is entered immediately following the last write cycle of any command sequence that initiates an ea. commands that initiate an ea are: ? word program ? program buffer to flash ? chip erase ? sector erase ? erase resume / program resume ? program resume enhanced method ? blank check ? lock register program ? password program ? ppb program
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 15 data sheet (preliminary) ? all ppb erase the data polling status word appears at all word locations in the device address space. when an ea is completed the data polling status aso is exited and the device address space returns to the address map mode where the ea was started. note that in future technology nodes the data poll ing status feature will not be supported. the user is strongly advised to use the status register to determine device status. 2.5 secure silicon region aso the secure silicon region (ssr) provides an extra fl ash memory area that can be programmed once and permanently protected from further changes i. e. it is a one time program (otp) area. the ssr is 1024-bytes in length. it consists of 512-bytes for factory locked secure silicon region and 512-bytes for customer locked secure silicon region. the sector address supplied during the secure sili con entry command selects the flash memory array sector that is overlaid by the secure silicon region addr ess map. the ssr is overlaid starting at location 0 in the selected sector. use of the sector 0 address is re commended for future compatibility. while the ssr aso is entered the content of all other sectors is undefi ned. locations above the maximum defined address of the ssr aso to the maximum address of th e selected sector have undefined data. 2.6 sector protection control 2.6.1 lock register aso the lock register aso contains a single word of ot p memory. when the aso is entered the lock register appears at all word locations in the device address spac e. however, it is recommended to read or program the lock register only at location 0 of the device address space for future compatibility. 2.6.2 persistent protect ion bits (ppb) aso the ppb aso contains one bit of a flash memory array for each sector in the de vice. when the ppb aso is entered, the ppb bit for a sector appea rs in the least significant bit (l sb) of each word in the sector. reading any word in a sector displays a word where th e lsb indicates the non-volatile protection status for that sector. however, it is recomm ended to read or program th e ppb only at word location 0 of the sector for future compatibility. if the bit is 0 the sector is protected against progra mming and erase operations. if the bit is 1 the sector is not protected by the ppb. the sector may be prot ected by other features of asp. 2.6.3 ppb lock aso the ppb lock aso contains a single bi t of volatile memory. t he bit controls whether the bits in the ppb aso may be programmed or erased. if the bit is 0 the pp b aso is protected against programming and erase operations. if the bit is 1 the ppb aso is not protected. when the ppb lo ck aso is entered the ppb lock bit appears in the least significant bit (lsb) of each wo rd in the device address space. however, it is recommended to read or program the ppb lock only at word location 0 of the device for fu ture compatibility. 2.6.4 password aso the password aso contains four words of otp memo ry. when the aso is entered the password appears starting at address 0 in the device address space. all locations above the forth word are undefined. table 2.6 secure silicon region word address range content size (sa) + 0000h to 00ffh factory locked secure silicon region 512 bytes (sa) + 0100h to 01ffh customer locked secure silicon region 512 bytes (sa) + 01ffh to ffffh undefined 127 kbytes
16 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 2.6.5 dynamic protection bits (dyb) aso the dyb aso contains one bit of a volatile memory ar ray for each sector in the device. when the dyb aso is entered, the dyb bit for a sector appears in the leas t significant bit (lsb) of each word in the sector. reading any word in a sector displays a word where th e lsb indicates the non-volatile protection status for that sector. however, it is recommended to read, set, or clear the dyb only at word lo cation 0 of the sector for future compatibility. if the bit is 0 the sector is protected against progra mming and erase operations. if the bit is 1 the sector is not protected by the dyb. the sector may be pr otected by other features of asp.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 17 data sheet (preliminary) 3. data protection the device offers several features to prevent malicious or accidental erasure of any sector via hardware means. 3.1 device protection methods 3.1.1 power-up write inhibit reset#, ce#, we#, and, oe# are ig nored during power-on re set (por). during por, the device can not be selected, will not accept commands on the rising edge of we#, and does not drive outputs. the host interface controller (hic) and embedded algorithm controlle r (eac) are reset to their standby states, ready for reading array data, during por. ce#, we#, and oe# must go to v ih before the end of por (t vcs ). at the end of por the device conditions are: ? all internal configuration information is loaded, ? the device is in read mode, ? the status register is at default value, ? all bits in the dyb aso are set to un-protect all sectors, ? the write buffer is loaded with all 1?s, ? the eac is in the standby state. 3.1.2 low v cc write inhibit when v cc is less than v lko , the hic does not a ccept any write cycles and the eac resets. this protects data during v cc power-up and power-down. the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 3.2 command protection embedded algorithms are initiated by writing comma nd sequences into the eac command memory. the command memory array is not readable by the host syst em and has no aso. each host interface write is a command or part of a command sequence to the device . the eac examines the address and data in each write transfer to determine if t he write is part of a legal comma nd sequence. when a legal command sequence is complete the eac will initiate the appropriate ea. writing incorrect address or data values , or writing them in an improper s equence, will generally result in the eac returning to its standby state. however, such an improper command sequenc e may place the device in an unknown state, in which case t he system must write the reset comma nd, or possibly pr ovide a hardware reset by driving the reset# signal low, to return the eac to its standby stat e, ready for random read. the address provided in each write may contain a bit pa ttern used to help identify the write as a command to the device. the upper portion of the address may also select the sector address on which the command operation is to be performed. the sector address (sa) includes a max through a16 flash address bits (system byte address signals a max through a17). a command bit pattern is located in a10 to a0 flash address bits (system byte address signals a11 through a1). the data in each write may be: a bit pattern used to help identify the write as a command, a code that identifies the command operation to be performed, or supply information needed to perform the operation. see table 6.1 on page 54 for a listing of all commands accepted by the device. 3.3 secure silicon region (otp) the secure silicon region (ssr) provides an extra fl ash memory area that can be programmed once and permanently protected from further changes i. e. it is a one time program (otp) area. the ssr is 1024 bytes in length. it consists of 512 bytes for factory locked secure silicon region and 512 bytes for customer locked secure silicon region.
18 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 3.4 sector protection methods 3.4.1 write protect signal if wp# = v il , the lowest or highest address sector is prot ected from program or er ase operations independent of any other asp configuration. whether it is the lo west or highest sector depends on the device ordering option (model) selected. if wp# = v ih , the lowest or highest address sector is not protected by the wp# signal but it may be protected by other aspects of asp c onfiguration. wp# has an internal pull-up; when unconnected, wp# is at v ih . 3.4.2 asp advanced sector protection (asp) is a set of independe nt hardware and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. this se ction describes the various methods of protecting data stored in the memory array. an overview of these methods is shown in figure 3.1 . figure 3.1 advanced sector protection overview every main flash array sector has a non-volatile (ppb) and a volatile (dyb) protection bit associated with it. when either bit is 0, the sector is prot ected from program an d erase operations. the ppb bits are protected from program and erase when the ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit, persis tent protection and password protection. the persistent protection me thod sets the ppb lock to 1 during por or hardware reset so that the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. p ass word method (dq2) per s i s tent method (dq1) lock regi s ter (one time progr a mm ab le) ppb lock bit 1,2, 3 64- b it p ass word (one time protect) 1 = ppb s unlocked 0 = ppb s locked memory arr a y s ector 0 s ector 1 s ector 2 s ector n-2 s ector n-1 s ector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n per s i s tent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dyn a mic protection bit (dyb) 6,7, 8 6. 0 = s ector protected, 1 = s ector unprotected. 7. protect effective only if corre s ponding ppb i s ? 1 ? ( u nprotected). 8 . vol a tile bit s : def au lt s to us er choice u pon power- u p ( s ee ordering option s ). 4. 0 = s ector protected, 1 = s ector unprotected. 5. ppb s s et (progr a mmed) individ ua lly, bu t cle a red (er as ed) collectively 1. bit i s vol a tile, a nd def au lt s to ? 1 ? on re s et. 2. progr a mming to ? 0 ? lock s a ll ppb s to their c u rrent s t a te. 3 . once progr a mmed to ? 0 ? , re qu ire s h a rdw a re re s et to u nlock. 3 . n = highe s t addre ss s ector.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 19 data sheet (preliminary) there is no command in the persist ent protection method to set the ppb lock bit therefore the ppb lock bit will remain at 0 until the next power-off or hardware re set. the persistent protection method allows boot code the option of changing sector prot ection by programming or erasing the ppb, then protec ting the ppb from further change for the remainder of normal system operatio n by clearing the ppb lock bit. this is sometimes called boot-code controlled sector protection. the password method clears the ppb lo ck bit to 0 during por or hardwa re reset to protect the ppb. a 64- bit password may be permanently programmed and hi dden for the password method. a command can be used to provide a password for comparison with the hidden password. if the password matches the ppb lock bit is set to 1 to unprotect the ppb. a command can be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. the selection of the ppb lock management method is made by programming otp bits in the lock register so as to permanently select the method used. the lock register also contains otp bits, for protecting the ssr. the ppb bits are erased so that all main flash arra y sectors are unprotected when shipped from spansion. the secured silicon region can be factory protect ed or left unprotected dep ending on the ordering option (model) ordered. 3.4.3 ppb lock the persistent protection bit lock is a volatile bit fo r protecting all ppb bits. when cleared to 0, it locks all ppbs and when set to 1, it allows the ppbs to be changed. there is only one ppb lock bit per device. the ppb lock command is used to clear the bit to 0. the ppb lock bit must be cleared to 0 only after all the ppbs are configured to the desired settings. in persistent protection m ode, the ppb lock is set to 1 during por or a hardware reset. when cleared, no software command sequence can set the ppb lock, only another hardware reset or power-up can set the ppb lock bit. in the password protection mode, the ppb lock is cleared to 0 during por or a hardware reset. the ppb lock can only set to 1 by the password unlock command sequence. 3.4.4 persistent prot ection bits (ppb) the persistent protecti on bits (ppb) are located in a separate nonvolatile flash a rray. one of the ppb bits is assigned to each sector. when a ppb is 0 its related se ctor is protected from program and erase operations. the ppb are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time. the ppb may be erased and reprogrammed up to 1k times. preprogrammi ng and verification prior to erasure are handled by the eac. programming a ppb bit requires the ty pical word programming time. duri ng a ppb bit programming operation or ppb bit erasing, data polling status dq6 toggle bit i will toggle until the operation is complete. erasing all the ppbs requires typical sector erase time. if the ppb lock is 0, the ppb program or eras e command does not execute and times-out without programming or erasing the ppb. the protection state of a ppb for a given sector can be ve rified by writing a ppb st atus read command when entered in the ppb aso. 3.4.5 dynamic protection bits (dyb) dynamic protection bits are volatile and unique for eac h sector and can be individually modified. dybs only control protection for sectors th at have their ppbs cleared. by issu ing the dyb set or clear command sequences, the dyb are set to 1 or cleared to 0, thus placing each sector in the unprotected or protected state respectively. this feature allows software to easily protect sectors agai nst inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dyb can be set to 1 or cleared to 0 as often as needed.
20 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 3.4.6 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprotected and protection can be changed by a simple command. the protection state defaults to unprotected after a power cycle or hardware reset. ? dynamically locked ? a sector is protected and pr otection can be changed by a simple command. the protection state is not saved across a power cycle or hardware reset. ? persistently locked ? a sector is protected and protection c an only be changed if the ppb lock bit is set to 1. the protection state is non-volatile and saved across a power cycle or hardware reset. changing the protection state requires programming or erase of the ppb bits. 3.4.7 lock register the lock register holds the non-volatile otp bits for controlling protection of the ssr, and determining the ppb lock bit management method (protection mode). the secure silicon region (ssr) protection bits must be used with caution, as once locked, there is no procedure available for unlocking the protected portion of the secure silicon region and none of the bits in the protected secure silicon region memory space can be modified in any way. once the secure silicon region area is protected, any further attempts to progr am in the area will fail with status indicating the area being programmed is protected. the region 1 indicator bit is located in the lock register at bit location 0 and region 2 in bit location 6. as shipped from the factory, all devices default to the persistent protection method, with all sectors unprotected, when power is applied. the device progr ammer or host system can then choose which sector protection method to use. programmi ng either of the following two, one-time programmable, non-volatile bits, locks the part permanently in that mode: ? persistent protection mode lock bit (dq1) ? password protection mode lock bit (dq2) table 3.1 sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected - ppb and dyb are changeable 1 1 0 protected - ppb and dyb are changeable 1 0 1 protected - ppb and dyb are changeable 1 0 0 protected - ppb and dyb are changeable 0 1 1 unprotected - ppb not changeable, dyb is changeable 0 1 0 protected - ppb not changeable, dyb is changeable 0 0 1 protected - ppb not changeable, dyb is changeable 0 0 0 protected - ppb not changeable, dyb is changeable table 3.2 lock register bit default value name 15-9 1 reserved 8 0 reserved 7 x reserved 6 1 ssr region 1 (customer) lock bit 5 1 reserved 4 1 reserved 3 1 reserved 2 1 password protection mode lock bit 1 1 persistent protection mode lock bit 0 0 ssr region 0 (factory) lock bit
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 21 data sheet (preliminary) if both lock bits are selected to be programmed at th e same time, the operation will abort. once the password mode lock bit is programmed, the persistent mode lo ck bit is permanently disabled and no changes to the protection scheme are allowed. sim ilarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. if the password mode is chosen, the password must be programmed prior to setting the corresponding lock register bit. after the password prot ection mode lock bit is programmed, a power cycle, hardware reset, or ppb lock bit set command is required to set the ppb lock bit to 0 to protect the ppb array. the programming time of the lock register is the same as the typical word programming time. during a lock register programming ea, data polling status dq6 toggle bit i will toggle until the programming has completed. the system can also determine the status of the lock register programming by reading the status register. see status register on page 36 for information on these status bits. the user is not required to program dq 2 or dq1, and dq6 or dq0 bits at th e same time. this allows the user to lock the ssr before or after choosing the device protection scheme. 3.4.8 persistent protection mode the persistent protection me thod sets the ppb lock to 1 during por or hardware reset so that the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no command in the persist ent protection method to set the ppb lock bit to 1 therefore the ppb lock bit will remain at 0 until the next power-off or hardware reset. 3.4.9 password protection mode 3.4.9.1 ppb password protection mode ppb password protection mode allows an even higher level of security than the persistent sector protection mode, by requiring a 64-bit password for setting the ppb lock. in addition to this password requirement, after power up and reset, the ppb lock is cleared to 0 to ensu re protection at power-up. successful execution of the password unlock command by enteri ng the entire password sets the ppb lock to 1, allowing for sector ppb modifications. password protection notes: ? the password program command is only capable of programming 0?s. ? the password is all 1?s when shipped from spansion. it is located in its own memory space and is accessible through the use of the password program and password read commands. ? all 64-bit password combinations are valid as a password. ? once the password is programmed and verified, the password mode locking bit must be set in order to prevent reading the password. ? the password mode lock bit, once programmed, preven ts reading the 64-bit password on the data bus and further password programming. all further prog ram and read commands to the password region are disabled and these commands are ignored. there is no means to verify what the password is after the password protection mode lock bit is programmed. password verification is only allowed before selecting the password protection mode. ? the password mode lock bit is not erasable. ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation on a prot ected sector. the status register will return to the ready state with the program st atus bit set to 1 and the sector lock status bit set to 1 indicating a failed programming operation due to a locked sector. in this case it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid password. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock command, and dq6 toggling, ? the device requires approximately 100 s for setting the ppb lock after the valid 64-bit password is given to the device.
22 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) ? the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to co rrectly match a password. the ea status checking methods may be used to determine when the eac is ready to accept a new password command. ? if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 23 data sheet (preliminary) 4. read operations 4.1 asynchronous read each read access may be made to any location in the memory (random access). each random access is self- timed with the same latency from ce# or address to valid data (t acc or t ce ). 4.2 page mode read each random read accesses an entire 32-byte page in parallel. subsequent reads within the same page have faster read access speed. the page is selected by the higher address bits ( a max -a4), while the specific word of that page is selected by the least significant address bits a3-a 0. the higher address bits are kept constant and only a3-a0 changed to select a different word in the same page. this is an asynchronous access with data appearing on dq15-dq0 when ce# remains low, oe# remains low, and the asynchronous page access time (t pac c ) is satisfied. if ce# goes high and returns low for a subsequent access, a random read access is performed and time is required (t acc or t ce ).
24 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 5. embedded operations 5.1 embedded algorithm controller (eac) the eac takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change t he non-volatile memory state. this frees the host system from any need to manage the program and erase processes. there are four eac operation categories: ? standby (read mode) ? address space switching ? embedded algorithms (ea) ? advanced sector protection (asp) management 5.1.1 eac standby in the standby mode current consumption is greatl y reduced. the eac enters its standby mode when no command is being processed and no embedded algorithm is in progress. if the device is deselected (ce# = high) during an embedded algorithm, the devi ce still draws active current until the operation is completed (i cc3 ). i cc4 in dc characteristics on page 69 represents the standby current specification when both the host interface and eac are in their standby state. 5.1.2 address space switching writing specific address and data sequences (command sequences) swit ch the memory device address space from the main flash array to one of the address space overlays (aso). embedded algorithms operate on the information visible in the currently active (entered) aso. the system continues to have access to the aso until the system issues an aso exit command, performs a hardware reset, or until power is removed from the device. an aso ex it command switches fr om an aso back to the main flash array address space. the commands acce pted when a particular aso is entered are listed between the aso enter and exit commands in the command definitions table. see command summary on page 54 for address and data requirements for all command sequences. 5.1.3 embedded algorithms (ea) changing the non-volatile data in the memory arra y requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the device internal embedded algorithm controller (eac). the main algorithms perfo rm programming and erase of the main array data and the aso?s. the host system writes command codes to th e flash device address space. the eac receives the commands, performs all the necessary steps to comple te the command, and provides status information during the progress of an ea. 5.2 program and erase summary flash data bits are erased in parallel in a large group called a sector. the erase operation places each data bit in the sector in the logical 1 st ate (high). flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state. a data bit of 0 cannot be programmed back to a 1. a succeeding read shows that the data is still 0. only erase operations can convert a 0 to a 1. programming the same word location more than once with different 0 bits will result in the logical and of the previous data and the new data being programmed. the duration of program and er ase operations is shown in embedded algorithm performance table on page 44 . program and erase operations may be suspended. ? an erase operation may be suspended to allow either prog ramming or reading of anot her sector (not in the erase sector) in the erase operation. no other eras e operation can be started during an erase suspend.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 25 data sheet (preliminary) ? a program operation may be suspended to allow reading of another location (not in the line being programmed). ? no other program or erase operation may be started during a suspended program operation - program or erase commands will be ignored during a suspended program operation. ? after an intervening program operation or read access is complete the suspended erase or program operation may be resumed. ? program and erase operations may be interrupted as often as necessary but in order for a program or erase operation to progress to completion there must be some periods of time between resume and the next suspend commands greater than or equal to t prs or t ers in embedded algorithm performance table on page 44 . ? when an embedded algorithm (ea) is complete, the ea c returns to the operation state and address space from which the ea was started (erase suspend or eac standby). the system can determine the status of a program or eras e operation by reading the status register or using data polling status. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. any commands written to the device during the em bedded program algorithm are ignored except the program suspend, and status read command. any commands written to the device during the em bedded erase algorithm are ignored except erase suspend and status read command. a hardware reset immediately terminates any in prog ress program / erase operation and returns to read mode after t rph time. the terminated operation should be reinitiated once the device has returned to the idle state, to ensure data integrity. for performance and reliability reasons reading and progra mming is internally done on full 32 byte pages. i cc3 in dc characteristics on page 69 represents the active current specification for a write (embedded algorithm) operation. 5.2.1 program granularity the s29gl-s supports two methods of programming, word or write buffer programming. each page can be programmed by either method. pa ges programmed by different methods may be mixed within a line. word programming examines the data word supplied by the command and programs 0?s in the addressed memory array word to match the 0?s in the command data word. write buffer programming examines the write buffer and programs 0?s in the addressed memory array page to match the 0?s in the write buffer. the write buffer does not need to be completely filled with data. it is allowed to program as little as a single bit, several bits , a single word, a few words, a page, multiple pages, or the entire buffer as one programming op eration. use of the write buffer method reduces host system overhead in writing program comm ands and reduces memory device internal overhead in programming operations to make write buffer programming more ef ficient and thus faster than programming individual words with the word programming command. 5.2.2 incremental programming the same word location may be programmed more than once, by either the word or write buffer programming methods, to incrementally change 1?s to 0?s.
26 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 5.3 command set 5.3.1 program methods 5.3.1.1 word programming word programming is used to program a single word anywhere in the main flash memory array. the word programming command is a four-write- cycle sequence. the program command sequence is initiated by writing two unlock writ e cycles, followed by th e program set up command. the program address and data are written next, which in turn initiate the embedded word program algorithm. the system is not required to provide further controls or timing. the device automatically generates the program pulses and verifies the programmed cell margin internally. when the embedded word program algorithm is complete, the eac then returns to its standby mode. the system can determine the status of the program operation by using data polling status, reading the status register, or monitoring the ry/by# output. see status register on page 36 for information on these status bits. see data polling status on page 37 for information on these status bits. see figure 5.1 on page 26 for a diagram of the programming operation. any commands other than program su spend written to the device during the embedded program algorithm are ignored. note that a hardware reset (reset# = v il ) immediately terminates the programming operation returns to read mode after t rph time. to ensure data integrity, the program command sequence should be reinitiated once the device has completed the hardware reset operation. the word programming command may also be used when the ssr aso is entered. a modified version of the word programming command, without unlock write cycles, is used for programming when entered into the lock register, password, and ppb asos. the same command is used to change volatile bits when entered in to the ppb lock, and dyb asos. see table 6.1 on page 54 for program command sequences. figure 5.1 word program operation 5.3.1.2 write buffer programming a write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (line). thus, a full write buffer programming operat ion must be aligned on a line boundary. programming operations of less than a full 512 bytes may start on any word boundary but may not cross a line boundary. at the start of a write buff er programming operation all bit locations in the buffer are all 1?s (ffffh words) thus any locations not loaded will retain the existing data. see product overview on page 9 for information on address map. s tart write progr a m comm a nd s e qu ence d a t a poll from s y s tem verify word? l as t addre sss ? increment addre ss em b edded progr a m a lgorithm in progre ss progr a mming completed no no ye s ye s
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 27 data sheet (preliminary) write buffer programming allows up to 512-bytes to be programmed in one operation. it is possible to program from 1 bit up to 512-bytes in each write buffe r programming operation. it is recommended that a multiple of pages be written and each page written only once. for the very best performance, programming should be done in full lines of 512-bytes aligned on 512-byte boundaries. write buffer programming is supported only in the main flash array or the ssr aso. the write buffer programming operation is initiated by first writing two unlock cycles. this is followed by a third write cycle of the write to bu ffer command with the sector address (sa), in which programming is to occur. next, the system writes the number of word lo cations minus 1. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the sector address must match in the wr ite to buffer command and the write word count command. the sector to be programmed must be unlocked (unprotected). the system then writes the starting a ddress / data combination. this starting address is the first address / data pair to be programmed, and sele cts the write-buffer-line address. the sector address must match the write to buffer sector address or the operation will abort and return to the initiating state. all subsequent address / data pairs must be in sequential order. all wr ite buffer addresses must be within the same line. if the system attempts to load data outside this range, the operation will abort and return to the initiating state. the counter decrements for each data load operation. no te that while counting down the data writes, every write is considered to be data being loaded into the wr ite buffer. no commands are possible during the write buffer loading period. the only way to stop loading the writ e buffer is to write with an address that is outside the line of the programming operation. this invalid address will immediately abort the write to buffer command. once the specified number of write buffer locations has been loaded, the system must then write the program buffer to flash command at the sector address. the device then goes busy. the embedded program algorithm automatically programs and verifies the data for th e correct data pattern. th e system is not required to provide any controls or timings during these operat ions. if an incorrect number of write buffer locations have been loaded the operation will abort and return to the initiating state. the abort occurs when anything other than the program buffer to flash is written wh en that command is expected at the end of the word count. the write-buffer embedded programming operati on can be suspended using the program suspend command. when the embedded program algorithm is comp lete, the eac then returns to the eac standby or erase suspend standby state where the programming operation was started. the system can determine the status of the program operation by using data polling status, reading the status register, or monitoring the ry/by# output. see status register on page 36 for information on these status bits. see data polling status on page 37 for information on these status bits. see figure 5.2 on page 28 for a diagram of the programming operation. the write buffer programming sequence will be aborted under the following conditions: ? load a word count value greater than the buffer size (255). ? write an address that is outside the line provided in the write to buffer command. ? the program buffer to flash command is not issued af ter the write word count number of data words is loaded. when any of the conditions that cause an abort of write buffer command occur the abort will happen immediately after the offending condition, and will indicate a program fail in the status register at bit location 4 (psb = 1) due to write buffer abor t bit location 3 (wbasb = 1). the nex t successful program operation will clear the failure status or a cle ar status register may be i ssued to clear the psb status bit. the write buffer programming sequence can be stopped by the following: hardware reset or power cycle. however, these using either of these methods may l eave the area being programmed in an intermediate state with invalid or unstable data values. in this case the sa me area will need to be reprogrammed with the same data or erased to ensure data values are properly programmed or erased.
28 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) figure 5.2 write buffer programming oper ation with data polling status notes: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 2. if this flowchart location was reached because dq5 = 1, then the device failed. if this flowchart location was reached becaus e dq1 = 1, then the write buffer operation was aborted. in either case the proper reset command must be written to the device to return th e device to read mode. write-buffer-programming-abort-rest if dq1 = 1, either software reset or write-buffer-programming-abort- reset if dq5 = 1. 3. see table 6.1, command definitions on page 54 for the command sequence as required for write buffer programming. 4. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ? write to b u ffer ? comm a nd s ector addre ss write ? word co u nt ? to progr a m - 1 (wc) s ector addre ss write s t a rting addre ss /d a t a wc = 0? abort write to b u ffer oper a tion? write to a different s ector addre ss write to b u ffer aborted. m us t write ? write-to-b u ffer abort re s et ? comm a nd s e qu ence to ret u rn to read mode. write next addre ss /d a t a p a ir wc = wc - 1 write progr a m b u ffer to fl as h confirm, s ector addre ss re a d dq7-dq0 with addr = la s t loaded addre ss dq7 = d a t a ? dq5 = 1? dq1 = 1? re a d dq7-dq0 with addr = la s t loaded addre ss dq7 = d a t a ? fail or abort (note 2) pa ss no ye s (note 4) no no no no no ye s ye s ye s ye s ye s
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 29 data sheet (preliminary) figure 5.3 write buffer programming operation with status register notes: 1. see table 6.1, command definitions on page 54 for the command sequence as required for write buffer programming. 2. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ? write to b u ffer ? comm a nd s ector addre ss write ? word co u nt ? to progr a m - 1 (wc) s ector addre ss write s t a rting addre ss /d a t a wc = 0? abort write to b u ffer oper a tion? write to a different s ector addre ss write to b u ffer aborted. m us t write ? write-to-b u ffer abort re s et ? comm a nd s e qu ence to ret u rn to read mode. write next addre ss /d a t a p a ir wc = wc - 1 write progr a m b u ffer to fl as h confirm, s ector addre ss re a d s t a t us regi s ter drb s r[7] = 0? wba s b s r[ 3 ] = 1? p s b s r[4] = 0? progr a m f a il progr a m su cce ss f u l no ye s (note 2) no no no ye s ye s ye s no ye s progr a m ab orted d u ring write to b u ffer comm a nd s l s b s r[1] = 0? no ye s s ector locked error progr a m f a il
30 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) legend: sa = sector address (non-sector address bits are don't care. any address within the sector is sufficient.) wbl = write buffer location (must be within the boundaries of the write-buffer-line specified by the starting address.) wc =word count pd = program data 5.3.2 program suspend / program resume commands the program suspend command allows the system to inte rrupt an embedded programm ing operation so that data can read from any non-suspended line. when the program suspend command is written during a programming process, the device hal ts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are don't-c ares when writing the program suspend command. there are two commands available for program suspend. the legacy combined erase / program suspend command (b0h command code) and the separate prog ram suspend command (51h command code). there are also two commands for program resume. the lega cy combined erase / program resume command (30h command code) and the separate program resume command (50h command code). it is recommended to use the separate program suspend and resume comm ands for programming and use the legacy combined command only for erase suspend and resume. after the programming operation has been suspended, the system can read array data from any non- suspended line. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. after the program resume command is written, the devi ce reverts to programming and the status bits are updated. the system can determine the st atus of the program operation by reading the status register or using data polling. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. accesses and commands that are valid during program suspend are: ? read to any other non-erase-suspended sector ? read to any other non-program-suspended line ? status read command ? exit aso or command set exit ? program resume command the system must write the program resume command to exit the program sus pend mode and continue the programming operation. further writ es of the program resume comma nd are ignored. another program suspend command can be written after the device has resumed programming. table 5.1 write buffer programming command sequence sequence address data comment issue unlock command 1 555/aaa aa issue unlock command 2 2aa/555 55 issue write to buffer command at sector address sa 0025h issue number of locations at sector address sa wc wc = number of words to program - 1 example: wc of 0 = 1 words to pgm wc of 1 = 2 words to pgm load starting address / data pair starting address pd selects write-buffer-page and loads first address/data pair. load next address / data pair wbl pd all addresses must be within the selected write-buffer- page boundaries, and have to be loaded in sequential order. load last address/data pair wbl pd all addresses must be within the selected write-buffer- page boundaries, and have to be loaded in sequential order. issue write buffer program confirm at sector address sa 0029h this command must follow the last write buffer location loaded, or the operation will abort. device goes busy.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 31 data sheet (preliminary) program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t prs in embedded algorithm controller (eac) on page 24 . program suspend and resume is not su pported while entered in an aso. whil e in program suspend entry into aso is not supported. 5.3.3 blank check the blank check command will confirm if the selected main flash array sector is erased. the blank check command does not allow for reads to the array during the blank check. reads to the array while this command is executing will return unknown data. to initiate a blank check on a sector, write 33h to address 555h in the sector, while the eac is in the standby state the blank check command may not be written while th e device is actively programming or erasing or suspended. use the status register read to confirm if the device is still busy and when complete if the sector is blank or not. bit 7 of the status register will show if the device is performing a blank check (similar to an erase operation). bit 5 of the status register will be cleared to 0 if the sector is erased and set to 1 if not erased. as soon as any bit is found to not be erased, the device will halt the operation and report the results. once the blank check is completed, the eac will return to the standby state. 5.3.4 erase methods 5.3.4.1 chip erase the chip erase function er ases the entire main flash memory array. the device do es not require the system to preprogram prior to erase. the embedded erase algo rithm automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase. after a successful chip erase, all locations within the device contain ffffh. the syst em is not required to pr ovide any controls or timi ngs during these operations. the chip erase command sequence is initiated by writ ing two unlock cycles, followed by a set up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. when the embedded erase algorithm is complete, the eac returns to the standby state. note that while the embedded erase operation is in progress, the system c an not read data from the device. the system can determine the status of the erase o peration by reading the status regist er or using data polling. refer to status register on page 36 for information on these st atus bits. refer to data polling status on page 37 for more information. once t he chip erase operation has begun, only a stat us read, hardware reset or power cycle are valid. all other commands ar e ignored. however, a hardware reset or po wer cycle immediately terminates the erase operation and returns to read mode after t rph time. if a chip erase operation is terminated, the chip erase command sequence must be re initiated once the device has returned to the idle state to ensure data integrity. see table 5.4 on page 44 , asynchronous write operations on page 76 and alternate ce# controlled write operations on page 82 for parameters and timing diagrams. sectors protected by the asp dyb and ppb lock bits will not be erased. see asp on page 18 . if a sector is protected during chip er ase, chip erase will skip the protected sector and continue with next sector erase. the status register erase status bit and sector lock bit are not set to 1 by a failed erase on a protected sector. 5.3.4.2 sector erase the sector erase function erases one sector in the memory array. the dev ice does not require the system to preprogram prior to erase. the em bedded erase algorithm aut omatically programs and verifies the entire sector for an all 0 data pattern prior to electrical erase. after a successful sector er ase, all locations within the erased sector contain ffff h. the system is not required to provid e any controls or timings during these operations. the sector erase command sequence is initia ted by writing two unlock cycles, followed by a set up command. two additional unlock write cycles are then fo llowed by the address of t he sector to be erased, and the sector erase command.
32 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) the system can determine the status of the erase operation by reading th e status register or using data polling. refer to status register on page 36 for information on these status bits. refer to data polling status on page 37 for more information. once the sector erase operation ha s begun, the status re gister read and erase suspend commands are valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation and returns to read mode after t rph time. if a sector erase opera tion is terminated, the sector erase command sequence must be reinitiated once the de vice has reset operation to ensure data integrity. see embedded algorithm controller (eac) on page 24 for parameters and timing diagrams. sectors protected by the asp dyb and ppb lock bits will not be erased. see asp on page 18 . figure 5.4 sector erase operation write unlock cycle s : addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h write s ector er as e cycle s : addre ss 555h, d a t a 8 0h addre ss 555h, d a t a aah addre ss 2aah, d a t a 55h s ector addre ss , d a t a 3 0h fail. write re s et comm a nd to ret u rn to re a ding a rr a y. pa ss . device ret u rn s to re a ding a rr a y. perform write oper a tion s t a t us algorithm unlock cycle 1 unlock cycle 2 ye s ye s no no done? er as e error? comm a nd cycle 1 comm a nd cycle 2 comm a nd cycle 3 s pecify fir s t s ector for er asu re error condition (exceeded timing limit s ) s t a t us m a y b e o b t a ined b y s t a t us regi s ter polling or d a t a polling method s .
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 33 data sheet (preliminary) 5.3.5 erase suspend / erase resume the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, the main flash array. this command is valid only during sector erase or program operation. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation and update the status bits. after the erase operation has been suspended, the pa rt enters the erase-suspe nd mode. the system can read data from or program data to the main flash array. reading at any address within erase-suspended sectors produces undetermine d data. the system can determ ine if a sector is active ly erasing or is erase- suspended by reading the status regist er or using data polling. refer to status register on page 36 for information on these stat us bits. refer to data polling status on page 37 for more information. after an erase-suspended program operation is complete , the eac returns to the erase-suspend state. the system can determine the status of the program operatio n by reading the status register, just as in the standard program operation. if a program failure occurs during erase suspend the cl ear or reset commands will return the device to the erase suspended state. erase will need to be resu med and completed before again trying to program the memory array. accesses and commands that are valid during erase suspend are: ? read to any other non-suspended sector ? program to any other non-suspended sector ? status read command ? enter dyb aso ? dyb set ? dyb clear ? dyb status read ? exit aso or command set exit ? erase resume command to resume the sector erase operat ion, the system must write the er ase resume command. the device will revert to erasing and the status bi ts will be updated. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. erase suspend and resume is not supported while entered in an aso. while in erase suspend entry into aso is not supported. 5.3.6 aso entry and exit 5.3.6.1 id-cfi aso the system can access the id-cfi aso by issuing th e id-cfi entry command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid and which sector's protection st ate is reported in word location 2h. see the detail description table 6.2 on page 57 . the id-cfi aso allows the following activities: ? read id-cfi aso, using the same sa as used in the entry command. ? read sector protection state at sector address (sa) + 2h. location 2h provides volatile information on the current state of sector protection for the sector addressed. bit 0 of the wo rd at location 2h shows the logical nand of the ppb and dyb bits re lated to the addressed sector such that if the sector is protected by either the ppb=0 or the dyb=0 bit for that sector the state sh own is protected. (1= sector protected, 0= sector unprotected). this protection state is shown only fo r the sa selected when entering id-cfi aso. reading other sa provides undefined data. to read a differen t sa protection state aso exit command must be used and then enter id-cfi aso again with the new sa.
34 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) ? aso exit. the following is a c source code example of using the cfi entry and exit f unctions. refer to the spansion low level driver user's guide (available on www.spansion.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)base_addr + 0x55 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ 5.3.6.2 status register aso when the status register read command is issued, the current status is captured by the register and the aso is entered. the first read access in the status re gister aso exits the aso and returns to the address space map in use when the status register read command was issued. no other command should be sent before reading the status to exit the status register aso. 5.3.6.3 secure silicon region aso the system can access the secure silicon region by issuing the secure silicon region entry command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid. the secure silicon region aso allows the following activities: ? read secure silicon regions, using the same sa as used in the entry command. ? program the customer secure silicon region using the word or write buffer programming commands. ? aso exit using legacy secure silicon exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.4 lock register aso the system can access the lock register by issuin g the lock register entry command sequence during read mode. this entry command does not use a sector address from t he entry command. the lock register appears at word location 0 in the device address space. all other locations in the device address space are undefined. the lock register aso allows the following activities: ? read lock register, using device address location 0. ? program the customer lock register using a modified word programming command. ? aso exit using legacy command set exit co mmand for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.5 password aso the system can access the password aso by issuing the password entry command sequence during read mode. this entry command does not use a sector ad dress from the entry comm and. the password appears at word locations 0 to 3 in the device address space. all other locations in the device address space are undefined. the password aso allows the following activities: ? read password, using device address location 0 to 3. ? program the password using a modified word programming command. ? unlock the ppb lock bit with the password unlock command. ? aso exit using legacy command set exit co mmand for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 35 data sheet (preliminary) 5.3.6.6 ppb aso the system can access the ppb aso by issuing the ppb entry command sequence during read mode. this entry command does not use a sector address from th e entry command. the ppb bit for a sector appears in bit 0 of all word locations in the sector. the ppb aso allows the following activities: ? read ppb protection status of a sector in bit 0 of any word in the sector. ? program the ppb bit using a modified word programming command. ? erase all ppb bits with the ppb erase command. ? aso exit using legacy command set exit co mmand for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.7 ppb lock aso the system can access the ppb lock aso by issuing the ppb lock entry command sequence during read mode. this entry command does not use a sector add ress from the entry command. the global ppb lock bit appears in bit 0 of all word locations in the device. the ppb lock aso allows the following activities: ? read ppb lock protection status in bit 0 of any word in the device address space. ? set the ppb lock bit using a modi fied word progra mming command. ? aso exit using legacy command set exit co mmand for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.8 dyb aso the system can access the dyb aso by issuing the dyb entry command sequence during r ead mode. this entry command does not use a sector address from the entry command. th e dyb bit for a sector appears in bit 0 of all word locations in the sector. the dyb aso allows the following activities: ? read dyb protection status of a sector in bit 0 of any word in the sector. ? set the dyb bit using a modified word programming command. ? clear the dyb bit using a modified word programming command. ? aso exit using legacy command set exit co mmand for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.9 software (command) reset / aso exit software reset is part of the command set (see table 6.1, command definitions on page 54 ) that also returns the eac to standby state and must be used for the following conditions: ? exit id/cfi mode ? clear timeout bit (dq5) for data polling when timeout occurs software reset does not affect ea mode. reset co mmands are ignored once programming or erasure has begun, until the operation is complete. software reset does not affect outputs; it serv es primarily to return to read mode from an aso mode or from a failed program or erase operation. software reset may cause a return to read mode from undefined states that might result from invalid command sequences. however, a hardware reset may be re quired to return to normal operation from some undefined states. there is no software reset latency requiremen t. the reset command is executed during the t wph period.
36 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 5.4 status monitoring there are three methods for monitoring ea status. prev ious generations of the s 29gl flash family used the methods called data polling and ready/busy# (ry/by#) signal. these methods ar e still supported by the s29gl-s family. one additiona l method is reading the status register. only the status register method will be supported in future technology nodes. 5.4.1 status register the status of program and erase operations is provided by a single 16-bit status regi ster. the status register read command is written followed by one read access of the status register info rmation. the contents of the status register is aliased (overlaid) in all locations of the device address space. the overlay is in effect for one read access, specifically the next read access that follows the status register read command. after the one status register access, the status register aso is exited. the ce# or oe# signal must go high following the status register read access for t ceph /t oeph time to return to the address s pace active at the time the status register read command was issued. the status register c ontains bits related to the re sults - success or failure - of the most recently completed embedded algorithms (ea): ? erase status (bit 5), ? program status (bit 4), ? write buffer abort (bit 3), ? sector locked status (bit 1), ? rfu (bit 0). and, bits related to the current state of any in process ea: ? device busy (bit 7), ? erase suspended (bit 6), ? program suspended (bit 2), the current state bits indica te whether an ea is in proce ss, suspended, or completed. the upper 8 bits (bits 15:8) are reserved. these have undefined high or low value that can change from one status read to another. these bits should be treated as don't care and ignored by any software reading status. the clear status register command will clear to 0 the re sults related bits of the st atus register but will not affect the current state bits.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 37 data sheet (preliminary) notes: 1. bits 15 thru 8, and 0 are reserved for future use and may disp lay as 0 or 1. these bits should be ignored (masked) when check ing status. 2. bit 7 is 1 when there is no embedded algorithm in progress in the device. 3. bits 6 thru 1 are valid only if bit 7 is 1. 4. all bits are put in their reset status by cold reset or warm reset. 5. bits 5, 4, 3, and 1 are cleared to 0 by the clear status register command or reset command. 6. upon issuing the erase suspend command, the user must continue to read status until drb becomes 1. 7. essb is cleared to 0 by the erase resume command. 8. esb reflects success or failure of the most recent erase operation. 9. psb reflects success or failure of the most recent program operation. 10. during erase suspend, programming to the suspended sector, will cause program failure and set the program status bit to 1. 11. upon issuing the program suspend command, the user must continue to read status until drb becomes 1. 12. pssb is cleared to 0 by the program resume command. 13. slsb indicates that a program or erase operation failed because the sector was locked. 14. slsb reflects the status of the most recent program or erase operation. 5.4.2 data polling status during an active embedded algorithm the eac switches to the data polling aso to display ea status to any read access. a single word of status information is aliased in all locations of the device address space. in the status word there are several bits to determine the stat us of an ea. these are referred to as dq bits as they appear on the data bus during a read access while an ea is in progress. dq bits 15 to 8, dq4, and dq0 are reserved and provide undefined data. status monitoring software must mask the reserved bits and treat them as don't care. table 5.3 on page 41 and the following subsections describe the functions of the remaining bits. note that in future technology nodes the data poll ing status feature will not be supported. the user is strongly advised to use the status register to determine device status. 5.4.2.1 dq7: data# polling the data# polling bit, dq7, indicates to the host sys tem whether an embedded algorithm is in progress or has completed. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. note that the data# polling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. reading dat a# polling status on any word other than the last word to be programmed in the write-buffer- page will return false status information. during the embedded program algorithm, the device outputs on dq7 the complement of the data bit programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device out puts the data bit programmed to bit 7 of the last word programmed. in case of a program suspend, t he device allows only reading array data. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 20 s, then the device returns to reading array data. table 5.2 status register bit #15:876543210 bit description reserved device ready bit erase suspend status bit erase status bit program status bit write buffer abort status bit program suspend status bit sector lock status bit reserved bit name drb essb esb psb wbasb pssb slsb reset status x10000000 busy status invalid 0 invalid invalid invalid invalid invalid invalid invalid ready status x1 0=no erase in suspension 1=erase in suspension 0=erase successful 1=erase fail 0=program successful 1=program fail 0=program not aborted 1=program aborted during write to buffer command 0=no program in suspension 1=program in suspension 0=sector not locked during operation 1=sector locked error x
38 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) during the embedded erase or blank check algorithms, data# polling produces a 0 on dq7. when the algorithm is complete, or if the device enters the er ase suspend mode, data# polling produces a '1' on dq7. this is analogous to the complement / true datum output described for the embed ded program algorithm: the erase function changes all the bits in a sector to '1'; prior to this, the device outputs the complement or '0'. the system must provide an address withi n the sector selected for erasure to read valid status information on dq7. after an erase command sequence is writ ten, if the sector selected for eras ing is protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. when the system detects dq7 has c hanged from the complement to tr ue data, it can read valid data at dq15-dq0 on the following read cycles. this is bec ause dq7 may change asynchronously with dq6-dq0 while output enable (oe#) is asserted low. this is illustrated in figure 10.15 on page 81 . table 5.3 on page 41 shows the outputs for data# polling on dq7. figure 5.2 on page 28 shows the data# polling algorithm use in write buffer programming. valid dq7 data polling status may only be read from: ? the address of the last word loaded into the write buffer for a write buffer programming operation; ? the location of a single word programming operation; ? or a location in a sector being erased or blank checked. figure 5.5 data# polling algorithm note: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 5.4.2.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the program suspend or erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation). during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles). when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if the sector selected for erasing is protected, dq6 toggles for approximately 100 s, then the eac returns to standby (read mode). if the selected sector is not protected, the embedded erase algorithm er ases the unprotected sector. the system can use dq6 and dq2 to gether to determine whether a sector is actively erasing or erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 s tart re a d dq7 -dq0 - fail dq7 = d a t a ? no ye s dq5 = 1? no ye s dq7 = d a t a ? no ye s pa ss re a d dq 7 -dq0
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 39 data sheet (preliminary) toggles. when the device enters the program suspend m ode or erase suspend mode, dq6 stops toggling. however, the system must also us e dq2 to determine which sectors are erasing, or erase-suspended. alternatively, the system can use dq7 (see dq7: data# polling on page 37 ). dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 5.3 on page 41 shows the outputs for toggle bit i on dq6. figure 5.6 on page 40 shows the toggle bit algorithm in flowchart form, and the reading toggle bits dq6/dq2 on page 39 explains the algorithm. figure 5.6 on page 40 shows the toggle bit timing diagrams. figure 5.2 on page 28 shows the differences between dq2 and dq6 in graphical form. see also dq2: toggle bit ii on page 39 . 5.4.2.3 dq3: sector erase timer after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. see sector erase on page 31 for more details. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1, the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. table 5.3 on page 41 shows the status of dq3 relative to the other status bits. 5.4.2.4 dq2: toggle bit ii toggle bit ii on dq2, when used with dq6, indicates whet her a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within the sector selected for erasure. (the system may use either oe# or ce# to control the read cycles). but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase suspend, but cannot dist inguish if the sector is selected for eras ure. thus, both status bits are required for sector and mode information. refer to table 5.3 on page 41 to compare outputs for dq2 and dq6. figure 5.5 on page 38 shows the toggle bit algorithm in flowchart form, and the reading toggle bits dq6/ dq2 on page 39 explains the algorithm. see also figure 5.6 on page 40 shows the toggle bit timing diagram. figure 5.2 on page 28 shows the differences between dq2 and dq6 in graphical form. 5.4.2.5 reading toggle bits dq6/dq2 refer to figure 5.5 on page 38 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the previous value. if the toggle bit is not toggling, the device has completed t he program or erases operation. th e system can read array data on dq15-dq0 on the fo llowing read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whether th e value of dq5 is high (see dq5: exceeded timing limits on page 40 ). if it is, the system should then determine again whet her the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bi t is no longer toggling, the device has successfully completed the program or erase operation. if it is st ill toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 5.6 on page 40 ).
40 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) figure 5.6 toggle bit program notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 5.4.2.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produ ces a '1'. this is a failure condition th at indicates the program or erase cycle was not successfully completed. the syste m must issue the reset command to return the device to reading array data. when a timeout occurs, the software must send a reset command to clear the timeout bit (dq5) and to return the eac to read array mode. in this case, it is possible that the flash will continue to communicate busy for up to 2 s after the reset command is sent. s tart re a d dq7 -dq0 (note 1) er as e/progr a m oper a tion not complete toggle bit = toggle? ye s no dq5 = 1? no ye s re a d dq7 -dq0 twice (note s 1, 2) toggle bit = toggle? ye s no er as e/progr a m oper a tion complete re a d dq7 -dq0
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 41 data sheet (preliminary) 5.4.2.7 dq1: write-to-buffer abort dq1 indicates whether a write-to-buf fer operation was aborted. under t hese conditions dq1 produces a '1'. the system must issue the write-to-buffer-abort-rese t command sequence to return the eac to standby (read mode) and the status register failed bits are cleared. see write buffer programming on page 26 for more details. notes: 1. dq5 switches to '1' when an embedded program or embedded er ase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 40 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details 3. data are invalid for addresses in a program suspended line. 4. dq1 indicates the write-to-buffer abort status during write-buffer-programming operations. 5.5 error types and clearing procedures there are three types of errors reported by the emb edded operation status methods. depending on the error type, the status reported and procedure for clearing the error status is different. following is the clearing of error status: ? if an aso was entered before the error the device remains entered in the aso awaiting aso read or a command write. ? if an erase was suspended before the error the device returns to the erase suspended state awaiting flash array read or a command write. ? otherwise, the device will be in standby stat e awaiting flash array read or a command write. 5.5.1 embedded operation error if an error occurs during an embedded operation (progr am, erase, blank check, or password unlock) the device (eac) remains busy. the ry/by# output remains lo w, data polling status contin ues to be overlaid on all address locations, and the status register shows ready with valid status bits. the device remains busy until the error status is detected by the host system st atus monitoring and the error status is cleared. during embedded algorithm error status the data polling status will show the following: ? dq7 is the inversion of the dq7 bit in the last word loaded into the write buffer or last word of the password in the case of the password unlock command. dq7 = 0 for an erase or blank check failure ? dq6 continues to toggle ? dq5 = 1; failure of the embedded operation table 5.3 data polling status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 00 reading within erasing sector 0 toggle 0 1 toggle n/a 0 reading outside erasing sector 0 toggle 0 1 no toggle n/a 0 program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non-program suspended sector data data data da ta data data 1 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle n/a 1 reading within non-erase suspend sector data data data data data data 1 programming within non-erase suspended sector dq7# toggle 0 n/a n/a n/a 0 write-to- buffer (note 4) busy state dq7# toggle 0 n/a n/a 0 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 0 abort state dq7# toggle 1 n/a n/a 1 0
42 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 continues to toggle, independent of the address used to read status ? dq1 = 1; write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) during embedded algorithm error status the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase suspended during the ea error ? sr[5] = 1 on erase or blank check error; else = 0 ? sr[4] = 1 on program or password unlock error; else = 0 ? sr[3] = 1; write buffer abort ? sr[2] = 1; program suspended ? sr[1] = 1; protected sector ? sr[0] = x; rfu, treat as don?t care (masked) when the embedded algorithm error status is detected, it is necessary to cl ear the error status in order to return to normal operation, with ry/by# high, ready for a new read or co mmand write. the error status can be cleared by writing: ? reset command ? status register clear command commands that are accepted during embedded algorithm error status are: ? status register read ? reset command ? status register clear command 5.5.2 protection error if an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or otp area) the device (eac) goes busy for a perio d of 20 to 100 s then returns to normal operation. during the busy period the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows not ready with invalid status bits (sr[7] = 0). during the protection error status busy period the data polling status will show the following: ? dq7 is the inversion of the dq7 bit in the last word loaded into the write buffer. dq7 = 0 for an erase failure ? dq6 continues to toggle, independent of the address used to read status ? dq5 = 0; to indicate no failure of the embedded operation during the busy period ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 continues to toggle, independent of the address used to read status ? dq1 = 1; write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) commands that are accepted during the protection error status busy period are: ? status register read when the busy period ends the device returns to normal operation, the data pollin g status is no longer overlaid, ry/by# is high, and the status register shows ready with valid status bits. the device is ready for flash array read or write of a new command.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 43 data sheet (preliminary) after the protection error status busy period the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase susp ended after the protection error busy period ? sr[5] = 1 on erase error, else = 0 ? sr[4] = 1 on program error, else = 0 ? sr[3] = 0; program not aborted ? sr[2] = 0; no program in suspension ? sr[1] = 1; error due to attempti ng to change a protected location ? sr[0] = x; rfu, treat as don?t care (masked) commands that are accepted after the protection error status busy period are: ? any command 5.5.3 write bu ffer abort if an error occurs during a write to buffer comma nd the device (eac) remains busy. the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. the device remains busy until the error status is detected by the host system status monitoring and th e error status is cleared. during write to buffer abort (w ba) error status the data polling status will show the following: ? dq7 is the inversion of the dq7 bit in th e last word loaded into the write buffer ? dq6 continues to toggle, independent of the address used to read status ? dq5 = 0; to indicate no failure of the programming o peration. wba is an error in the values input by the write to buffer command before the programming operation can begin ? dq4 is rfu and should be treated as don?t care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 does not toggle as no erase is in progress ? dq1 = 1: write buffer abort error ? dq0 is rfu and should be treated as don?t care (masked) during embedded algorithm error status the status register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be erase suspended during the wba error status ? sr[5] = 0; erase successful ? sr[4] = 1; programming related error ? sr[3] = 1; write buffer abort ? sr[2] = 0; no program in suspension ? sr[1] = 0; sector not locked during operation ? sr[0] = x; rfu, treat as don?t care (masked) when the wba error status is detected, it is necessary to clear the error status in order to return to normal operation, with ry/by# high, ready for a new read or co mmand write. the error status can be cleared by writing: ? write buffer abort reset command ? clears the status register and returns to normal operation ? status register clear command commands that are accepted during embedded algorithm error status are: ? status register read
44 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) ? reads the status register and returns to wba busy state ? write buffer abort reset command ? status register clear command 5.6 embedded algorithm performance table notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. under worst case conditions of 90c, v cc = 2.70v, 100,000 cycles, and a random data pattern. 4. effective write buffer specification is based upon a 512-byte write buffer operation. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to execute the bus-cycle sequence for the program command. see table 6.1, command definitions on page 54 for further information on command definitions. table 5.4 embedded algorithm characteristics parameter typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 200 1100 ms includes pre-programming prior to erasure (note 5) single word programming time (note 1) 150 400 s buffer programming time 2-byte (note 1) 150 s 32-byte (note 1) 180 64-byte (note 1) 200 128-byte (note 1) 240 256-byte (note 1) 320 512-byte 420 750 sector programming time 128 kb (full buffer programming) 108 192 ms (note 6) erase suspend/erase resume (t esl ) 40s program suspend/program resume (t psl ) 40s erase resume to next erase suspend (t ers ) 100 s minimum of 60 ns but typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs ) 100 s minimum of 60 ns but typical periods are needed for program to progress to completion. blank check 6.2 8.5 ms nop (number of program-operations, per line) 256
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 45 data sheet (preliminary) 5.6.1 command state transitions notes: 1. state will automatically move to read state at the completion of the operation. 2. also known as erase suspend/program suspend legacy method. table 5.5 read command state transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 blank check cfi entry address ra xh x555h x555h x555h (sa)555h (sa)55h data rd 00f0h x70h x71h xaah x33h x98h read - read read readsr (read) read readul1 - cfi read protect = false blck readsr-(return)------ table 5.6 read unlock command state transition current state command and condition read status register read enter unlock 2 word program entry write to buffer enter erase enter id (auto- select) entry ssr entry lock register entry pass- word aso entry ppb entry ppb lock entry dyb aso entry address ra x555h x2aah x555h (sa)xh x555h (sa)555h (sa)555h x555h x555h x555h x555h x555h data rd x70h x55h xa0h x25h x80h x 90h x88h x40h x60h xc0h x50h xe0h readul1 - readu l1 readsr (read) readu l2 ---- - ----- readul2 read protect = tr u e readu l2 readsr (read) - --- cfi -- pp - -- read protect = false pg1 wb er ssr lr ppblb dyb read protect = false and lr(8) = 0 ppb table 5.7 erase state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 unlock 2 chip erase start sector erase start erase suspend enhanced method (2) address ra xh x555h x555h x555h x2aah x555h (sa)xh xh data rd 00f0h x70h x71h xaah x55h x10h x30h xb0h er - er - readsr (read) -erul1---- erul1 - erul1 - readsr (read) --erul2--- erul2 - erul2 - readsr (read) - - - cer ser - cer (1) -cer- ersr (cer) ------ ser (1) sr(7) = 0 ser - ersr (ser) - ----esr (es) sr(7) = 1 read read blck (1) sr(7) = 0 blck - ersr (blck) - ----- sr(7) = 1 read read ersr - (return)
46 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) note: 1. state will automatically move to es state by t esl . note: 1. also known as erase resume/program resume legacy method. table 5.8 erase suspend state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 sector erase start address ra xh x555h x555h x555h (sa)xh data rd 00f0h x70h x71h xaah x30h esr (1) - esr ersr (esr) - - - es sr(7) = 0 es es essr (es) es esul1 - sr(7) = 1 ser essr -(return)- ---- table 5.9 erase suspend unlock state command transition current state command and condition read software reset / aso exit status register read enter unlock 1 word program entry write to buffer enter write- to- buffer- abort reset start erase resume enhanced method (1) dyb aso entry not a valid ?write-to-buffer- abort reset? command address ra xh x555h x2aah x555h (sa)xh x555h xh x555h not x555h xh not x2aah xh data rd 00f0h x70h x55h xa0h x25h 00f0h x30h xe0h xh not 00f0h xh not x55h esul1 - esul1 - essr (es) esul2 - - - - - - - -- sr(3) = 1 espg espg dq(1) = 1 esul2 - esul2 es essr (es) - espg1 es_wb - ser - -- -- read protect = false esdyb sr(3) = 1 - es - espg espg dq(1) = 1 table 5.10 erase suspend - dyb state command transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit dyb set/ clear entry password word count address ra xh x555h x555h xh xh xh xh data rd 00f0h x70h x71h x90h 0000h xa0h 0003h esdyb - esdyb es essr (esdyb) esdyb esdybext - esdybset - esdybset - esdybset - - - - - - - esdybext - esdybext - - - - es - es
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 47 data sheet (preliminary) note: 1. also known as erase suspend/program suspend legacy method. notes: 1. state will automatically mo ve to esps state by t psl . 2. also known as erase resume/program resume legacy method. table 5.11 erase suspend - program command state transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 erase suspend enhanced method (1) program suspend enhanced method write data address ra xh x555h x555h x555h xh xh xh data rd 00f0h x70h x71h xaah xb0h x51h xh es_wb wc > 256 or sa sa es_wb - - - - - - espg wc 256 and sa = sa es_wb_ d es_wb_d wc < 0 or write buffer write buffer es_wb_d - - - - - - espg wc > 0 and write buffer = write buffer es_wb_ d espg1 - espg1 - - - - - - espg espg sr(7) = 0 espg - espgsr (espg) -- espsr (espg) espsr (espg) espg sr(7) = 1 es es esul1 espgsr - (return) - - - - - - (return) table 5.12 erase suspend - program suspe nd command state transistion current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 unlock 2 erase resume enhanced method (2) program resume enhanced method address ra xh x555h x555h x555h x2aah xh xh data rd 00f0h x70h x71h xaah x55h x30h x50h espsr (1) - espsr - espgsr (espsr) ----- esps - esps esps espssr (essp) esps espsul1 - espg espg espssr - (return) - - - - - - - espsul1 - espsul1 - espssr (esps) - - espsul2 - - espsul2 - espsul2 - espssr (esps) - - - espg espg
48 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) notes: 1. state will automatically move to read state at the completion of the operation. 2. also known as erase suspend/program suspend legacy method. notes: 1. state will automatically move to ps state by t psl . 2. also known as erase resume/program resume legacy method. table 5.13 program state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 program buffer to flash (confirm) erase suspend enhanced method (2) program suspend enhanced method write data address ra xh x555h x555h x555h (sa)xh xh xh xh data rd 00f0h x70h x71h xaah x29h xb0h x51h xh wb wc > 256 or sa sa wb------- pg wc 256 and sa = sa wb_d wb_d write buffer write buffer wb_d------- pg wc = 0 pbf wc > 0 and write buffer = write buffer wb_d pbf - - - - - - pg - - pg pg1-pg1------- pg pg (1) sr(7) = 0 pg - pgsr (pg) -- - psr (pg) psr (pg) pg sr(7) = 1 read read wbul1 - - sr(7) = 1 and sr(1) = 0 table 5.14 program unlock state command transition current state command and condition read software reset / aso exit status register read enter unlock 2 not a valid ?write-to-buffer-abort reset? command address ra xh x555h x2aah not x555h xh not x2aah xh data rd 00f0h x70h x55h xh not 00f0h xh not x55h wbul1 - wbul1 - - wbul2 - - -- sr(3) = 1 pg pg dq(1) = 1 wbul2 - wbul2 read - - -- -- sr(3) = 1 pg pg dq(1) = 1 pgsr-(return)------- table 5.15 program suspend state command transition current state command and condition read status register read enter status register clear erase resume enhanced method (2) program resume enhanced method address ra x555h x555h xh xh data rd x70h x71h x30h x50h psr (1) - psr pgsr (psr) - - - ps - ps pssr (ps) ps pg pg pssr - (return) - - - -
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 49 data sheet (preliminary) table 5.16 lock register state command transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit ppb lock bit set entry password word count address ra xh x555h x555h xh xh xh xh data rd 00f0h x70h x71h x90h 0000h xa0h 0003h lr - lr read lrsr (lr) lr lrext - lrpg1 - lrpg1-lrpg1------- lrpg - lrpg - lrsr (lrpg) ----- lrsr-(return)------- lrext - lrext - - - - read - read table 5.17 cfi state command transition current state command and condition read software reset / aso exit status register read enter status register clear address ra xh x555h x555h data rd 00f0h x70h x71h cfi - cfi read cfisr (cfi) cfi cfisr - (return) - - - table 5.18 secure silicon sector state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 address ra xh x555h x555h x555h data rd 00f0h x70h x71h xaah ssr - ssr read ssrsr (ssr) ssr ssrul1 table 5.19 secure silicon sector unlock state command transition current state command and condition read software reset / aso exit status register read enter unlock 2 word program entry write to buffer enter comman d set exit entry not a valid ?write-to-buffer-abort reset? command address ra xh x555h x2aah x555h (sa)xh x555h not x555h xh not x2aah xh data rd 00f0h x70h x55h xa0h x25h x90h xh not 00f0h xh not x55h ssrul1 - ssrul1 read ssrsr (ssr) ssrul2----- -- dq(1) = 1 ssrpg ssrpg sr(3) = 1 ssrul2 - ssrul2 ssr - - ssrpg1 ssr_wb ssrext -- -- dq(1) = 1 ssrpg ssrpg sr(3) = 1
50 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) table 5.20 secure silicon sector program state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 command set exit address ra xh x555h x555h x555h xh data rd 00f0h x70h x71h xaah 0000h ssrpg1 - ssrpg1 - - ssrpg1 - - ssr_wb wc > 256 or sa sa ssr_wb----- wc 256 and sa = sa ssr_wb_d wc < 0 or write buffer write buffer ssr_wb_d----- wc > 0 and write buffer = write buffer ssrpg sr(7) = 0 ssrpg - ssrsr (ssrpg) - - - sr(7) = 1 ssr sr(7) = 1 and dq(1) = 0 read dq(1) = 1 --ssrul1 sr(3) = 1 ssrsr - (return) - - - - - ssrext - ssrext - ssrsr (ssr) - - read table 5.21 password protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear password aso unlock enter password aso unlock start command set exit entry command set exit program entry password word count address ra xh x555h x555h 0h 0h xh xh xh xh data rd 00f0h x70h x71h x25h x29h x90h 0000h xa0h 0003h pp - pp read ppsr (pp) pp ppwb25 - ppext - pppg1 - ppwb25-ppwb25--------ppd ppd wc > 0 ppd ---- - ---- wc 0 - pppg pppg1-pppg1--------- pppg - pppg - ppsr (pppg) ------- ppsr-(return)--------- ppext-ppext------read--
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 51 data sheet (preliminary) table 5.22 non-volatile protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry dyb set start all ppb erase enter all ppb erase start address ra xh x555h x555h xh xh xh (sa)xh xh 0h data rd 00f0h x70h x71h x90h 0000h xa0h 0000h x80h x30h ppb - ppb read ppbsr (ppb) ppb ppbext - ppbpg1 - ppbpg1 - ppbpg1 - ppbpg1 read - - - ppbpg - ppb - ppber ppbpg sr(7) = 0 ppbpg - ppbsr (ppbpg) - ------ sr(7) = 1 read read ppber sr(7) = 0 ppber - ppbsr (ppber) - ------ sr(7) = 1 read read ppbsr-(return)--------- ppbext - ppbext ----read---- table 5.23 ppb lock bit command state transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry address ra xh x555h x555h xh xh xh data rd 00f0h x70h x71h x90h 0000h xa0h ppblb - ppblb read ppblbsr (ppblb) ppblb ppblbext - ppblbset ppblbsr-(return)------ ppblbset - ppblbset - - - - ppblb - lr(2) = 0 and lr(5) = 0 ppblbext - ppblbext - - - - read - table 5.24 volatile sector protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry dyb set start dyb clear start address ra xh x555h x555h xh xh xh (sa)xh (sa)xh data rd 00f0h x70h x71h x90h 0000h xa0h 0000h 0001h dyb - dyb read dybsr (dyb) dyb dtbext - dybset - - dybsr-(return)-------- dybset - dybset - - - - - - dyb dyb dybext - dybext - - - - read - - -
52 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) table 5.25 state transition definitions (sheet 1 of 2) current state command transition definition blck table 5.7 blank check cer table 5.7 chip erase start cfi table 5.17 id (autoselect) cfisr table 5.17 id (autoselect) - status register read dyb table 5.24 dyb aso dybext table 5.24 dyb aso - command exit dybset table 5.24 dyb aso - set dybsr table 5.24 dyb aso - status register read er table 5.7 erase enter ersr table 5.7 erase - status register read erul1 table 5.7 erase - unlock cycle 1 erul2 table 5.7 erase - unlock cycle 2 es table 5.8 erase suspended esdyb table 5.10 erase suspended - dyb aso esdybext table 5.10 erase suspended - dyb command exit esdybset table 5.10 erase suspended - dyb set/clear espg table 5.11 erase suspended - program espgsr table 5.11 erase suspended - program - status register read espg1 table 5.11 erase suspended - word program esps table 5.12 erase suspended - program suspended espsr table 5.12 erase suspended - program suspend espssr table 5.12 erase suspended - program suspend - status register read espsul1 table 5.12 erase suspended - program suspend - unlock 1 espsul2 table 5.12 erase suspended - program suspend - unlock 2 esr table 5.8 erase suspend request essr table 5.8 erase suspended - status register read esul1 table 5.9 erase suspended - unlock cycle 1 esul2 table 5.9 erase suspended - unlock cycle 2 es_wb table 5.11 erase suspended - write to buffer es_wb_d table 5.11 erase suspended - write to buffer data lr table 5.16 lock register lrext table 5.16 lock register - command exit lrpg table 5.16 lock register - program lrpg1 table 5.16 lock register - program start lrsr table 5.16 lock register - status register read pbf table 5.13 page buffer full pg table 5.13 program pgsr table 5.14 program - status register read pg1 table 5.13 word program pp table 5.21 password aso ppb table 5.22 ppb ppber table 5.22 ppb - erase ppbext table 5.22 ppb - command exit ppblb table 5.23 ppb lock bit ppblbext table 5.23 ppb lock bit - command exit ppblbset table 5.23 ppb lock bit - set ppblbsr table 5.23 ppb lock bit - status register read ppbpg table 5.22 ppb - program
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 53 data sheet (preliminary) ppbpg1 table 5.22 ppb - program request ppbsr table 5.22 ppb - status register read ppd table 5.21 password aso - data ppext table 5.21 password aso - command exit pppg table 5.21 password aso - program pppg1 table 5.21 password aso - program request ppsr table 5.21 password aso - status register read ps table 5.15 program suspended psr table 5.15 program suspend request pssr table 5.15 program suspended - status register read ppwb25 table 5.21 password aso - unlock read table 5.5 read array readsr table 5.5 read status register readul1 table 5.6 read - unlock cycle 1 readul2 table 5.6 read - unlock cycle 2 ser table 5.7 sector erase start ssr table 5.18 secure silicon ssrext table 5.20 secure silicon - command exit ssrpg table 5.20 secure silicon - program ssrpg1 table 5.20 secure silicon - word program ssrsr table 5.20 secure silicon - status register read ssrul1 table 5.19 secure silicon - unlock cycle 1 ssrul2 table 5.19 secure silicon - unlock cycle 2 ssr_wb table 5.20 secure silicon - write to buffer ssr_wb_d table 5.20 secure silicon - write to buffer - write data wb table 5.13 write to buffer wbul1 table 5.14 write buffer - unlock cycle 1 wbul2 table 5.14 write buffer - unlock cycle 2 wb_d table 5.13 write to buffer write data table 5.25 state transition definitions (sheet 2 of 2) current state command transition definition
54 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 6. software interface reference 6.1 command summary table 6.1 command definitions (sheet 1 of 3) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset/aso exit (notes 7 , 16 )1xxxf0 status register read 2 555 70 xxx rd status register clear 1 555 71 word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 11) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend legacy method (note 9) erase suspend enhanced method 1xxx b0 erase resume/program resume legacy method (note 10) erase resume enhanced method 1xxx 30 program suspend enhanced method 1xxx 51 program resume enhanced method 1xxx 50 blank check 1 (sa) 555 33 id-cfi (autoselect) aso id (autoselect) entry 3 555 aa 2aa 55 (sa) 555 90 cfi enter (note 8) 1 (sa) 55 98 id-cfi read 1 xxx rd reset/aso exit (notes 7 , 16 ) 1xxx f0 secure silicon regi on command definitions secure silicon region (ssr) aso ssr entry 3 555 aa 2aa 55 (sa) 555 88 read (note 6) 1 ra rd word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 11) 3 555 aa 2aa 55 555 f0 ssr exit (note 11) 4 555 aa 2aa 55 555 90 xx 0 reset/aso exit (notes 7 , 16 ) 1xxxf0
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 55 data sheet (preliminary) lock register command set definitions lock register aso lock register entry 3 555 aa 2aa 55 555 40 program (note 15) 2 xxx a0 xxx pd read (note 15) 1 0 rd command set exit (notes 12 , 16 ) 2xxx90xxx0 reset/aso exit (notes 7 , 16 ) 1xxx f0 password protection command set definitions password aso password aso entry 3 555 aa 2aa 55 555 60 program (note 14) 2xxx a0 pwa x pwdx read (note 13) 4 0 pwd0 1 pwd1 2 pwd2 3 pwd 3 unlock 7 0 25 0 3 0 pwd0 1 pwd 1 2pwd23 pwd 3 029 command set exit (notes 12 , 16 ) 2xxx90xxx0 reset/aso exit (notes 7 , 16 ) 1xxx f0 non-volatile sector protect ion command set definitions ppb (non-volatile sector protection) ppb entry 3 555 aa 2aa 55 555 c0 ppb program (note 17) 2 xxx a0 sa 0 all ppb erase (note 17) 2xxx80030 ppb read (note 17) 1 sa rd (0) command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 16 ) 1xxx f0 global non-volatile sector protection freeze command set definitions ppb lock bit ppb lock entry 3 555 aa 2aa 55 555 50 ppb lock bit cleared 2 xxx a0 xxx 0 ppb lock status read (note 17) 1 xxx rd (0) command set exit (notes 12 , 16 ) 2xxx90xxx0 reset/aso exit (note 16) 1xxxf0 table 6.1 command definitions (sheet 2 of 3) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
56 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) legend: x = don't care. ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector selected. address bits a max -a16 uniquely select any sector. wbl = write buffer location. the address must be within the same line. wc = word count is the number of write buffer locations to load minus 1. pwax = password address for word0 = 00h, word1 = 01h, word2 = 02h, and word3 = 03h. pwdx = password data word0, word1, word2, and word3. notes: 1. see table 8.1, interface states on page 63 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle during read, id/cfi read (manufacturing id / device id), indicator bits, secure silicon region read, ssr lock read , and 2nd cycle of status register read . 4. data bits dq15-dq8 are don't care in command sequences, except for rd, pd, wc and pwd. 5. address bits a max -a11 are don't cares for unlock and command cycles, unless sa or pa required. ( a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the id-cfi (autoselect) mode, or if dq5 goes high (while the device is providing status data). 8. command is valid when device is ready to read array data or when device is in id-cfi (autoselect) mode. 9. the system can read and program/program suspend in non-erasing sectors, or enter the id-cfi aso, when in the erase suspend mo de. the erase suspend command is valid only during a sector erase operation. 10. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 11. issue this command sequence to return to read mode after det ecting device is in a write-to-buffer-abort state. important: th e full command sequence is required if resetting out of abort. 12. the exit command returns the device to reading the array. 13. the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 14. for pwdx, only one portion of the password can be programm ed per each a0 command. portions of the password must be programme d in sequential order (pwd0 - pwd3). 15. all lock register bits are one-time programmable. the program state = 0 and the erase state = 1. also, both the persistent p rotection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation aborts and returns the device to read mode. lock register bits that are reserved for future use are undefined and may be 0?s or 1's. 16. if any of the entry commands was issued, an exit command must be issued to reset the device into read mode. 17. protected state = 00h, unprotected state = 01h. the sector address for dyb set, dyb clear, or ppb program command may be any location within the sector - the lower order bits of the sector address are don't care. 6.2 device id and common flash interface (id-cfi) aso map the device id portion of the aso (word locations 0h to 0fh) provides manufacturer id, device id, sector protection state, and basic featur e set information for the device. volatile sector protection command set definitions dyb (volatile sector protection) aso dyb aso entry 3 555 aa 2aa 55 555 e0 dyb set (note 17) 2 xxx a0 sa 0 dyb clear (note 17) 2 xxx a0 sa 1 dyb status read (note 17) 1 sa rd (0) command set exit (notes 12 , 16 ) 2xxx90xxx0 reset/aso exit (note 16) 1xxx f0 table 6.1 command definitions (sheet 3 of 3) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 57 data sheet (preliminary) id-cfi location 02h displays sector protection status for the sector selected by th e sector address (sa) used in the id-cfi enter command. to read the protection status of more than one sector it is necessary to exit the id aso and enter the id aso using the new sa. t he access time to read location 02h is always t acc and a read of this location requires ce# to go high before the read and return low to initiate the read (asynchronous read access). page mode read between loca tion 02h and other id loca tions is not supported. page mode read between id locations other than 02h is supported. for additional information see id-cfi aso on page 33 . table 6.2 id (autoselect) address map description address read data manufacture id (sa) + 0000h 0001h device id (sa) + 0001h 227eh protection verification (sa) + 0002h sector protection state (1= sector protected, 0= sector unprotected). this protection state is shown only for the sa selected when entering id-cfi aso. reading other sa provides undefined data. to read a different sa protection state aso exit command must be used and then enter id-cfi aso again with the new sa. indicator bits (sa) + 0003h dq15-dq08 = 1 (reserved) dq7 - factory locked secure silicon region 1 = locked, 0 = not locked dq6 - customer locked secure silicon region 1 = locked 0 = not locked dq5 = 1 (reserved) dq4 - wp# protects 0 = lowest address sector 1 = highest address sector dq3 - dq0 = 1 (reserved) rfu (sa) + 0004h reserved (sa) + 0005h reserved (sa) + 0006h reserved (sa) + 0007h reserved (sa) + 0008h reserved (sa) + 0009h reserved (sa) + 000ah reserved (sa) + 000bh reserved lower software bits (sa) + 000ch bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = classic command set bits 4-15 - reserved = 0 upper software bits (sa) + 000dh reserved device id (sa) + 000eh 2228h = 1 gb 2223h = 512 mb 2222h = 256 mb 2221h = 128 mb device id (sa) + 000fh 2201h
58 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) table 6.3 cfi query identification string word address data description (sa) + 0010h (sa) + 0011h (sa) + 0012h 0051h 0052h 0059h query unique ascii string ?qry? (sa) + 0013h (sa) + 0014h 0002h 0000h primary oem command set (sa) + 0015h (sa) + 0016h 0040h 0000h address for primary extended table (sa) + 0017h (sa) + 0018h 0000h 0000h alternate oem command set (00h = none exists) (sa) + 0019h (sa) + 001ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 6.4 cfi system interface string word address data description (sa) + 001bh 0027h v cc min. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001ch 0036h v cc max. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001dh 0000h v pp min. voltage (00h = no v pp pin present) (sa) + 001eh 0000h v pp max. voltage (00h = no v pp pin present) (sa) + 001fh 0008h typical timeout per single word write 2 n s (sa) + 0020h 0009h typical timeout for max multi-byte program, 2 n s (00h = not supported) (sa) + 0021h 0008h typical timeout per individual block erase 2 n ms (sa) + 0022h 0012h (1 gb) 0011h (512 mb) 0010h (256 mb) 000fh (128 mb) typical timeout for full chip erase 2 n ms (00h = not supported) (sa) + 0023h 0001h max. timeout for single word write 2 n times typical (sa) + 0024h 0002h max. timeout for buffer write 2 n times typical (sa) + 0025h 0003h max. timeout per individual block erase 2 n times typical (sa) + 0026h 0003h max. timeout for full chip erase 2 n times typical (00h = not supported) table 6.5 cfi device geometry definition word address data description (sa) + 0027h 001bh (1 gb) 001ah (512 mb) 0019h (256 mb) 0018h (128 mb) device size = 2 n byte; (sa) + 0028h 0001h flash device interface description 0 = x8-only, 1 = x16-only, 2 = x8/x16 capable (sa) + 0029h 0000h (sa) + 002ah 0009h max. number of byte in multi-byte write = 2 n (00 = not supported) (sa) + 002bh 0000h (sa) + 002ch 0001h number of erase block regions within device 1 = uniform device, 2 = boot device (sa) + 002dh 00xxh erase block region 1 information (refer to jedec jesd68-01 or jep137 specifications) 00ffh, 0003h, 0000h, 0002h =1 gb 00ffh, 0001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb (sa) + 002eh 000xh (sa) + 002fh 0000h (sa) + 0030h 000xh
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 59 data sheet (preliminary) (sa) + 0031h 0000h erase block region 2 information (refer to cfi publication 100) (sa) + 0032h 0000h (sa) + 0033h 0000h (sa) + 0034h 0000h (sa) + 0035h 0000h erase block region 3 information (refer to cfi publication 100) (sa) + 0036h 0000h (sa) + 0037h 0000h (sa) + 0038h 0000h (sa) + 0039h 0000h erase block region 4 information (refer to cfi publication 100) (sa) + 003ah 0000h (sa) + 003bh 0000h (sa) + 003ch 0000h table 6.6 cfi primary vendor-specific extended query (sheet 1 of 2) word address data description (sa) + 0040h 0050h query-unique ascii string ?pri? (sa) + 0041h 0052h (sa) + 0042h 0049h (sa) + 0043h 0031h major version number, ascii (sa) + 0044h 0035h minor version number, ascii (sa) + 0045h 001ch address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.13 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m floating gate 0110b = 0.09 m mirrorbit 0111b = 0.065 m mirrorbit eclipse 1000b = 0.065 m mirrorbit 1001b = 0.045 m mirrorbit (sa) + 0046h 0002h erase suspend 0 = not supported 1 = read only 2 = read and write (sa) + 0047h 0001h sector protect 00 = not supported x = number of sectors in smallest group (sa) + 0048h 0000h temporary sector unprotect 00 = not supported 01 = supported (sa) + 0049h 0008h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method (sa) + 004ah 0000h simultaneous operation 00 = not supported x = number of banks (sa) + 004bh 0000h burst mode type 00 = not supported 01 = supported table 6.5 cfi device geometry definition word address data description
60 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) (sa) + 004ch 0003h page mode type 00 = not supported 01 = 4 word page 02 = 8 word page 03=16 word page (sa) + 004dh 0000h acc (acceleration) supply minimum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004eh 0000h acc (acceleration) supply maximum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004fh 0004h (bottom) 0005h (top) wp# protection 00h = flash device without wp protect (no boot) 01h = eight 8 kb sectors at top and bottom with wp (dual boot) 02h = bottom boot device with wp protect (bottom boot) 03h = top boot device with wp protect (top boot) 04h = uniform, bottom wp protect (uniform bottom boot) 05h = uniform, top wp protect (uniform top boot) 06h = wp protect for all sectors 07h = uniform, top or bottom wp protect (sa) + 0050h 0001h program suspend 00 = not supported 01 = supported (sa) +0051h 0000h unlock bypass 00 = not supported 01 =supported (sa) + 0052h 0009h secured silicon sector (customer otp area) size 2 n (bytes) (sa) + 0053h 008fh software features bit 0: status register polling (1 = supported, 0 = not supported) bit 1: dq polling (1 = supported, 0 = not supported) bit 2: new program suspend/resume commands (1 = supported, 0 = not supported) bit 3: word programming (1 = supported, 0 = not supported) bit 4: bit-field programming (1 = supported, 0 = not supported) bit 5: autodetect programming (1 = supported, 0 = not supported) bit 6: rfu bit 7: multiple writes per line (1 = supported, 0 = not supported) (sa) + 0054h 0005h page size = 2 n bytes (sa) + 0055h 0006h erase suspend timeout maximum < 2 n (s) (sa) + 0056h 0006h program suspend timeout maximum < 2 n (s) (sa) + 0078h 0006h embedded hardware reset timeout maximum < 2 n (s) reset with reset pin (sa) + 0079h 0009h non-embedded hardware reset timeout maximum < 2 n (s) power on reset table 6.6 cfi primary vendor-specific extended query (sheet 2 of 2) word address data description
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 61 data sheet (preliminary) hardware interface 7. signal descriptions 7.1 address and data configuration address and data are connected in parallel (adp) via separate signal inputs and i/os. 7.2 input/output summary 7.3 versatile i/o feature the maximum output voltage level driven by, and input le vels acceptable to, the device are determined by the v io power supply. this supply allows the device to driv e and receive signals to and from other devices on the same bus having interface signal levels different from the de vice core voltage. 7.4 ready/busy# (ry/by#) ry/by# is a dedicated, open drain output pin that indicates whether an embedded algorithm, power-on reset (por), or hardware reset is in progress or comp lete. the ry/by# status is valid after the rising edge of the final we# pulse in a command sequence, when v cc is above v cc minimum during por, or after the table 7.1 i/o summary symbol type description reset# input hardware reset. at v il , causes the device to reset control logic to its standby state, ready for reading array data. ce# input chip enable. at v il , selects the device for data transfer with the host memory controller. oe# input output enable. at v il , causes outputs to be actively driven. at v ih , causes outputs to be high impedance (high-z). we# input write enable. at v il , indicates data transfer fr om host to device. at v ih , indicates data transfer is from device to host. a max -a0 input address inputs. a25-a0 for s29gl01gs a24-a0 for s29gl512s a23-a0 for s29gl256s a22-a0 for s29gl128s dq15-dq0 input/output data inputs and outputs wp# input write protect. at v il , disables program and erase functions in the lowest or highest address 64 kword (128 kb) sector of the device. at v ih , the sector is not protected. wp# has an internal pull up; when unconnected wp# is at v ih . ry/by# output - open drain ready/busy. indicates whether an embedded algorithm is in progress or complete. at v il , the device is actively engaged in an embedded algorithm such as erasing or programming. at high-z, the device is ready for read or a new command write - requires external pull-up resistor to detect the high-z state. multiple devices may have their ry/by# outputs tied together to detect when all devices are ready. v cc power supply core power supply v io power supply versatile io power supply. v ss power supply power supplies ground nc no connect not connected internally. the pin/ball location may be used in printed circuit board (pcb) as part of a routing channel. rfu no connect reserved for future use. not currently connecte d internally but the pin/ball location should be left unconnected and unused by pcb routing channel for future compatibility. the pin/ball may be used by a signal in the future. dnu reserved do not use. reserved for use by spansion. the pin/ball is connected internally. the input has an internal pull down resistance to v ss . the pin/ball can be left open or tied to v ss on the pcb.
62 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) falling edge of reset#. since ry/by# is an open drain output, several ry/ by# pins can be tied together in parallel with a pull up resistor to v io . if the output is low (busy), the device is actively erasing, programming, or resetting. (this includes programming in the erase suspend mode). if the output is high (ready), the device is ready to read data (including during the erase suspend mode), or is in the standby mode. table 5.3, data polling status on page 41 shows the outputs for ry/by# in each operation. if an embedded algorithm has failed (program / erase fail ure as result of max pulses or sector is locked), ry/by# will stay low (busy) until status register bits 4 and 5 are cleared and the reset command is issued. this includes erase or programming on a locked sector. 7.5 hardware reset the reset# input provides a hardware method of re setting the device to sta ndby state. when reset# is driven low for at least a period of t rp , the device immediately: ? terminates any operation in progress, ? exits any aso, ? tristates all outputs, ? resets the status register, ? resets the eac to standby state. ? ce# is ignored for the duration of the reset operation (t rph ). ? to meet the reset current specification (i cc5 ) ce# must be held high. to ensure data integrity any operation that was interrupt ed should be reinitiated once the device is ready to accept another command sequence.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 63 data sheet (preliminary) 8. signal protocols the following sections describe the host system interfac e signal behavior and timing for the 29gl-s family flash devices. 8.1 interface states table 8.1 describes the required value of each in terface signal for each interface state. legend: l = v il h = v ih x = either v il or v ih l/h = rising edge h/l = falling edge valid = all bus signals have stable l or h level modified = valid state different from a previous valid state available = read data is internally stored with output driver controlled by oe# notes: 1. we# and oe# can not be at v il at the same time. 2. read with output disable is a read initiated with oe# high. 3. automatic sleep is a read/write operation where data has been driven on the bus for an extended period, without ce# going hig h and the device internal logic has gone into standby mode to conserve power. 8.2 power-off with hardware data protection the memory is considered to be powered off when the core power supply (v cc ) drops below the lock-out voltage (v lko ). when v cc is below v lko , the entire memory array is prot ected against a program or erase operation. this ensures that no spurious alteration of the memory content can occur during power transition. during a power supply transition down to power-off, v io should remain less than or equal to v cc . if v cc goes below v rst (min) then returns above v rst (min) to v cc minimum, the powe r-on reset interface state is entered and the eac starts the cold reset embedded algorithm. table 8.1 interface states interface state v cc v io reset# ce# oe# we# a max -a0 dq15-dq0 power-off with hardware data protection < v lko v cc xxxxxhigh-z power-on (cold) reset v cc min v io min v cc xxxxxhigh-z hardware (warm) reset v cc min v io min v cc l x x x x high-z interface standby v cc min v io min v cc h h x x x high-z automatic sleep (notes 1 , 3 ) v cc min v io min v cc h l x x valid output available read with output disable (note 2) v cc min v io min v cc h l h h valid high-z random read v cc min v io min h l l h valid output valid page read v cc min v io min v cc hllh a max -a4 valid a3-a0 modified output valid write v cc min v io min v cc h l h l valid input valid
64 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 8.3 power conservation modes 8.3.1 interface standby standby is the default, low power, stat e for the interface while the device is not selected by the host for data transfer (ce# = high). all inputs are ignored in this st ate and all outputs except ry /by# are high impedance. ry/by# is a direct output of the eac, not controlled by the host interface. 8.3.2 automatic sleep the automatic sleep mode reduces device inte rface energy consumption to the sleep level (i cc6 ) following the completion of a random read access time. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. while in sleep mode, output data is latched and always available to the system. output of the data depends on the level of the oe# sig nal but, the automatic sleep mode current is independent of the oe# signal level. standard address access timings (t acc or t pac c ) provide new data when addresses are changed. i cc6 in dc characteristics on page 69 represents the automatic sleep mode current specification. automatic sleep helps reduce current consumption especially when the host system cl ock is slowed for power reduction. during slow system clock periods, read an d write cycles may extend many times their length versus when the system is operating at high speed. even though ce# may be low throughout these extended data transfer cycles, the me mory device host interface will go to the automatic sleep current at t acc + 30 ns. the device will remain at the automatic sleep current for t assb . then the device will transition to the standby current level. this keeps the memory at the automatic sleep or standby power level for most of the long duration data transfer cycles, rather than consuming full read power all the time that the memory device is selected by the host system. however, the eac operates independent of the automatic sleep mode of t he host interface and will continue to draw current during an active embedded algorithm. only when both the host interface and eac are in their standby states is the st andby level current achieved. 8.4 read 8.4.1 read with output disable when the ce# signal is asse rted low, the host system me mory controller begins a re ad or write data transfer. often there is a period at the beginn ing of a data transfer when ce# is low, address is valid, oe# is high, and we# is high. during this state a read access is assumed and the random read process is started while the data outputs remain at high impedance. if the oe # signal goes low, the interface transitions to the random read state, with data out puts actively driven. if the we# signal is asserted low, the interface transitions to the write state. note, oe# and we# sh ould never be low at the same time to ensure no data bus contention betwe en the host system and memory. 8.4.2 random (asynchronous) read when the host system interface selects the memory devic e by driving ce# low, the device interface leaves the standby state. if we# is high when ce# goes low , a random read access is st arted. the data output depends on the address map mode and the address prov ided at the time the read access is started. the data appears on dq15-dq0 when ce# is low, oe# is low, we# remains high, address remains stable, and the asynchronous access times ar e satisfied. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable ce# to valid data at the outputs. in order for the read data to be driven on to t he data outputs the oe# signal must be low at least the output enable time (t oe ) before valid data is available. at the completion of the random access time from ce# active (t ce ), address stable (t acc ), or oe# active (t oe ), whichever occurs latest, the data outputs will provi de valid read data from the currently active address map mode. if ce# remains low and any of the a max to a4 address signals change to a new value, a new random read access begins. if ce# remains low and oe# goes high the interface transitions to the read with output disable st ate. if ce# remains low, oe# goes high, and we# goes low, the interface transitions
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 65 data sheet (preliminary) to the write state. if ce# returns high, the interface goes to the standby state. back to back accesses, in which ce# remains low between accesses, requires an address change to initiate the second access. see asynchronous read operations on page 74 . 8.4.3 page read after a random read access is completed, if ce# remains low, oe# remains low, the a max to a4 address signals remain stable, and any of the a3 to a0 addr ess signals change, a new access within the same page begins. the page read co mpletes much faster (t pac c ) than a random read access. 8.5 write 8.5.1 asynchronous write when we# goes low after ce is low, there is a transition from one of the read stat es to the write state. if we# is low before ce# goes low, there is a transition from the standby state dire ctly to the write state without beginning a read access. when ce# is low, oe# is high, and we# goes low, a writ e data transfer begins. note, oe# and we# should never be low at the same time to ensure no data bus contention between the host system and memory. when the asynchronous write cycle timing requirements are met the we# can go high to capture the address and data values in to eac command memory. address is captured by the falling edge of we# or ce#, whichever occurs la ter. data is captured by the rising edge of we# or ce#, whichever occurs earlier. when ce# is low before we# goes low and stays low after we# goes high, the access is called a we# controlled write. when we# is high and ce# goes high, there is a transit ion to the standby state. if ce# remains low and we# goes high, there is a transi tion to the read with output disable state. when we# is low before ce# goes low and remains low after ce# goes high, the access is called a ce# controlled write. a ce# controlled wr ite transitions to the standby state. if we# is low before ce# goes low, the write transfer is started by ce# going low. if we# is low after ce# goes high, the address and data are capt ured by the rising edge of ce#. these cases are referred to as ce# controlled write state transitions. write followed by read accesses, in which ce# re mains low between accesses, requires an address change to initiate the following read access. back to back accesses, in wh ich ce# remains low between accesses, requires an address change to initiate the second access. the eac command memory array is not readable by the host system and has no aso. the eac examines the address and data in each write transfer to determine if the write is part of a legal command sequence. when a legal command sequence is complete the eac will initiate the appropriate ea. 8.5.2 write pulse ?g litch? protection noise pulses of less than 5 ns (typical) on we# will not initiate a write cycle. 8.5.3 logical inhibit write cycles are inhibite d by holding oe# at v il , or ce# at v ih , or we# at v ih . to initiate a write cycle, ce# and we# must be low (v il ) while oe# is high (v ih ).
66 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 9. electrical specifications 9.1 absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is -0.5v. duri ng voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 9.3 on page 68 . maximum dc voltage on input or i/o pins is v cc +0.5v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 9.4 on page 68 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 latchup characteristics this product complies with jedec standard jesd78c latchup testing requirements. 9.3 operating ranges 9.3.1 temperature ranges industrial (i) devices ambient temperature (t a ) -40c to +85c 9.3.2 power supply voltages v cc 2.7v to 3.6v v io 1.65v to v cc + 200 mv operating ranges define those limits between whic h the functionality of th e device is guaranteed. 9.3.3 power-up and power-down v cc must always be greate r than or equal to v io (v cc v io ). v io must track the rise and fall of v cc within 200 mv (v cc v io - 200 mv) when v io is below the v io minimum. the device ignores all inputs until a time delay of t vcs has elapsed after the moment that v cc and v io both rise above, and stay above, the minimum v cc and v io thresholds. during t vcs the device is performing power on reset operations. during power-down or voltage drops below v cc lockout maximum (v lko ), the v cc and v io voltages must drop below v cc reset (v rst ) minimum for a period of t pd for the part to initialize correctly when v cc and v io again rise to their operating ranges. see figure 9.2 on page 67 . if during a voltage drop the v cc stays above v lko maximum the part will stay initialized and will work correctly when v cc is again above v cc minimum. if the part locks up from improper init ialization, a hardware reset can be used to initialize the part correctly. normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). table 9.1 absolute maximum ratings storage temperature plastic packages -65c to +150c ambient temperature with power applied -65c to +125c voltage with respect to ground all pins (note 1) -0.5 v to (v cc + 0.5 v) output short circuit current (note 2) 100 ma v cc -0.5 v to +4.0 v v io -0.5 v to +4.0 v
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 67 data sheet (preliminary) note: 1. not 100% tested. figure 9.1 power-up figure 9.2 power-down and voltage drop table 9.2 power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required (note 1) 2.25 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur (note 1) 1.0 v t vcs v cc and v io minimum to first access (note 1) 300 s t pd duration of v cc v rst (min) (note 1) 15 s vcc (max) vcc (min) power supply voltage tim e t vcs full device access vcc v io (min) v io (max) <= 200 mv v io v cc (max) v cc (min) v cc and v io tim e v rst (min) t pd t vcs no device access allowed full device access allowed v lko (max)
68 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 9.3.4 input si gnal overshoot figure 9.3 maximum negative overshoot waveform figure 9.4 maximum positive overshoot waveform 20 n s 20 n s 20 n s ?2 .0 v v m a x il v min il 20 n s 20 n s 20 n s v io + 2.0 v v m a x ih v min ih
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 69 data sheet (preliminary) 9.4 dc characteristics notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for t acc + 30 ns. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or followi ng the stopping of an embedded operation, i cc7 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 9.3 dc characteristics parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max +0.02 1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max +0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (notes 1 , 2 ) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 vcc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 100 a i cc5 v cc reset current (notes 2 , 7 ) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (note 3) v ih = v io , v il = v ss , v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 150 a i cc7 v cc current during power up (notes 2 , 6 ) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (note 4) -0.5 0.2 x v io v v ih input high voltage (note 4) 0.7 x v io v io + 0.4 v v ol output low voltage (notes 4 , 8 ) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (note 4) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (note 2) 2.25 2.5 v v rst low v cc power on reset voltage (note 2) 1.0 v
70 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 9.5 capacitance characteristics notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 9.4 connector capacitance for fbga package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 12 14 pf c out output capacitance v out = 0 5 7 pf c in2 control pin capacitance v in = 0 8 13 pf table 9.5 connector capacitance for tsop package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 11 13 pf c out output capacitance v out = 0 4 6 pf c in2 control pin capacitance v in = 0 8 10 pf
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 71 data sheet (preliminary) 10. timing specifications 10.1 key to switching waveforms 10.2 ac test conditions figure 10.1 test setup note: 1. measured between v il max and v ih min. figure 10.2 input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) table 10.1 test specification parameter all speeds units output load capacitance, c l 30 pf input rise and fall times (note 1) 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t v io 0.0 v 0.5 v io 0.5 v io output measurement level input
72 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 10.3 power-on reset (por) and warm reset normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). notes: 1. not 100% tested. 2. timing measured from v cc reaching v cc minimum and v io reaching v io minimum to v ih on reset and v il on ce#. 3. reset# low is optional during por. if reset is asserted during por, the later of t rph , t vios , or t vcs will determine when ce# may go low. if reset# remains low after t vios , or t vcs is satisfied, t rph is measured from the end of t vios , or t vcs . reset must also be high t rh before ce# goes low. 4. v cc v io - 200 mv during power-up. 5. v cc and v io ramp rate can be non-linear. 6. sum of t rp and t rh must be equal to or greater than t rph. 10.3.1 power-on (cold) reset (por) during the rise of power supplies the v io supply voltage must remain less than or equal to the v cc supply voltage. however, the v io supply voltage must also be above v cc -200 mv until the v io supply voltage is > 1.65v i.e. the v io supply voltage must not lag behind the v cc supply voltage by more than 200 mv during power up, until the v io supply voltage reaches its minimum operating level. the cold reset embedded algorithm requires a relatively long, hundreds of s, period (t vcs ) to load all of the eac algorithms and default state from non-volatile me mory. during the cold reset period all control signals including ce# and reset# are ignored. if ce# is low during t vcs the device may draw higher than normal por current during t vcs but the level of ce# will not affect the co ld reset ea. ce# must be high by the end of t vcs . reset# may be high or low during t vcs . if reset# is low during t vcs it may remain low at the end of t vcs to hold the device in the hardware reset state. if reset# is high at the end of t vcs the device will go to the standby state. when power is first applied, with supply voltage below v rst then rising to reach operating range minimum, internal device configuration and warm reset activities ar e initiated. ce# is ignored for the duration of the por operation (t vcs or t vios ). reset# low during this por period is opt ional. if reset# is driven low during por it must satisfy the hardware reset parameters t rp and t rph . in which case the reset operations will be completed at the later of t vcs or t vios or t rph . during cold reset the device will draw i cc7 current. figure 10.3 power-up diagram table 10.2 power on and reset parameters parameter description limit value unit t vcs v cc setup time to first access (notes 1 , 2 )min300s t vios v io setup time to first access (notes 1 , 2 )min300s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 50 ns vcc vio reset# ce# trh tvios tvcs
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 73 data sheet (preliminary) 10.3.2 hardware (warm) reset during hardware reset (t rph ) the device will draw i cc5 current. when reset# continues to be held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. if a cold reset has not been completed by the device when reset# is asserted low after t vcs , the cold reset# ea will be performed instead of the warm reset#, requiring t vcs time to complete. see figure 10.4, hardware reset on page 73 . after the device has completed por and entered the st andby state, any later transition to the hardware reset state will initiate the warm reset embedded algo rithm. a warm reset is much shorter than a cold reset, taking tens of s (t rph ) to complete. during the warm reset ea, any in progress embedded algorithm is stopped and the eac is returned to its por stat e without reloading eac algorithms from non-volatile memory. after the warm reset ea completes, the inte rface will remain in the hardware reset state if reset# remains low. when reset# returns high the inte rface will transit to the standby state. if reset# is high at the end of the warm reset ea, the inte rface will directly transit to the standby state. if por has not been properly completed by the end of t vcs , a later transition to the hardware reset state will cause a transition to the power-on reset interface st ate and initiate the cold reset embedded algorithm. this ensures the device can complete a cold reset even if some aspect of the system power-on voltage ramp-up causes the por to not initiate or complete correctly. the ry/by# pin is low during cold or warm reset as an indication that the device is busy performing reset operations. hardware (warm) reset hardware reset is in itiated by the reset# signal going to v il . figure 10.4 hardware reset reset# ce# trp trph trh
74 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 10.4 ac characteristics 10.4.1 asynchronous read operations note: 1. not 100% tested. note: 1. not 100% tested. table 10.3 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v parameter description test setup speed options unit jedec std 100 110 120 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 100 110 ns 512 mb, 1 gb 110 120 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t pac c page access time 128 mb, 256 mb min 25 30 ns 512 mb, 1 gb 25 30 t glqv t oe output enable to output delay max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 20 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable ty p 5 s max 8 s table 10.4 read operation v io = v cc = 2.7v to 3.6v parameter description test setup speed option unit jedec std 90 100 110 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 90 100 ns 512 mb, 1 gb 100 110 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 90 100 ns 512 mb, 1 gb 100 110 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 90 100 ns 512 mb, 1 gb 100 110 t pa c c page access time 128 mb, 256 mb max 15 20 ns 512 mb, 1 gb 15 20 t glqv t oe output enable to output delay max 25 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable ty p 5 s max 8 s
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 75 data sheet (preliminary) figure 10.5 back to back read (t acc ) operation timing diagram figure 10.6 back to back read operation (t rc )timing diagram note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. figure 10.7 page read timing diagram note: word configuration: toggle a0, a1, a2, and a3. amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc
76 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 10.4.2 asynchronous write operations note: 1. not 100% tested. table 10.5 write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling or following status register read. min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# pulse width min 25 ns t whwl t wph we# pulse width high min 20 ns
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 77 data sheet (preliminary) figure 10.8 back to back write operation timing diagram figure 10.9 write to read (t acc ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs tch amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tdf tdf toh toh toh tas tah tds tdh twp tcs tsr_w
78 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) figure 10.10 write to read (t ce ) operation timing diagram figure 10.11 read to write (ce# v il ) operation timing diagram amax-a0 ce# oe# we# dq15-d0 tacc toe toeh tce tdf tdf toh toh toh tas tah tds tdh twp tcs tch tsr_w amax-a0 ce# oe# we# dq15-a0 tas tds tah tdh tch tacc tce toe toh toh tdf twp tghwl
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 79 data sheet (preliminary) figure 10.12 read to write (ce# toggle) operation timing diagram notes: 1. not 100% tested. 2. for 1-512-bytes programmed. 3. effective write buffer specification is base upon a 256-word write buffer operation 4. upon the rising edge of we#, must wait t sr/w before switching to another address. table 10.6 erase/program operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t whwh1 t whwh1 write buffer program operation typ 420 s effective write buffer program operation per word (notes 2 , 3 ) ty p 1 . 6 4 s program operation per word or page typ 150 s t whwh2 t whwh2 sector erase operation (note 1) ty p 2 0 0 m s t busy erase/program valid to ry/by# delay max 80 ns t sr/w latency between read and write operations (note 4) min 30 ns t esl erase suspend latency max 40 s t psl program suspend latency max 40 s t rb ry/by# recovery time min 0 s amax-a0 ce# oe# we# dq15-a0 tacc toe tce tas tcs tds tah tdh twp tch toh toh toh tdf tdf tghwl
80 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) figure 10.13 program operation timing diagram note: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 10.14 chip/sector erase operation timing diagram note: 1. sa = sector address (for sector erase), va = valid address for reading status data. oe# we# ce# d a t a addre ss e s t d s t ah t dh t wp pd t whwh1 t wc t a s t wph 555h pa pa re a d s t a t us d a t a (l as t two cycle s ) a0h t c s s t a t us d out progr a m comm a nd s e qu ence (l as t two cycle s ) ry/by# t rb t bu s y t ch pa oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data (last two cycles) ry/by# t rb t busy 30h in progress complete 55h
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 81 data sheet (preliminary) figure 10.15 data# polling timing diagram (during embedded algorithms) note: 1. va = valid address. illustration shows first status cycle a fter command sequence, last status read cycle, and array data read cycle. figure 10.16 toggle bit timing diagram (during embedded algorithms) note: 1. dq6 will toggle at any read address while the device is busy . dq2 will toggle if the address is within the actively erasing s ector. figure 10.17 dq2 vs. dq6 relationship diagram note: 1. the system may use oe# or ce# to toggle dq2 and dq6. dq2 toggles only when read at an address within the erase-suspended sect or. we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement valid data valid data t acc t rc status data tr u e oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# enter er as e er as e er as e enter er as e sus pend progr a m er as e sus pend re a d er as e sus pend re a d er as e we# dq6 dq2 er as e complete er as e sus pend sus pend progr a m re su me em b edded er as ing
82 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 10.4.3 alternate ce# contro lled write operations notes: 1. not 100% tested. figure 10.18 back to back (ce#) write operation timing diagram table 10.7 alternate ce# controlled write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t 0eph oe# high during toggle bit polling min 20 ns t ghek t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t elwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 20 ns amax-a0 ce# oe# we# dq15-dq0 tds tdh tas tah twc tcp tcph tws twh
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 83 data sheet (preliminary) figure 10.19 (ce#) write to read operation timing diagram amax-a0 ce# oe# we# dq15-d0 tacc toe tce tdf toh twc tas tah tds tdh tws twh toeh
84 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 11. physical interface 11.1 56-pin tsop 11.1.1 connection diagram figure 11.1 56-pin standard tsop notes: 1. pin 28, do not use (dnu), a device internal signal is connec ted to the package connector. t he connector may be used by spansi on for test or other purposes and is not intented for connection to any host system signal. do not use these connections for pcb signa l routing channels. 2. pin 27, 30, and 53 reserved for future use (rfu). 3 1 8 4 1 2 5 6 7 8 9 10 19 20 21 22 2 3 24 11 12 1 3 14 15 16 17 46 45 4 8 47 44 4 3 42 40 41 54 5 3 55 56 52 51 50 49 3 9 38 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 56-pin t s op 25 26 27 2 8 29 a15 a1 8 a14 a1 3 a12 a11 a10 a9 a 8 a19 a20 we# re s et# a21 wp# ry/by# a17 a7 a6 a5 a2 3 a22 a4 a 3 a2 a1 rfu dnu a24 a25 dq10 a16 rfu v ss dq15 dq7 dq14 dq6 dq2 dq9 dq1 dq 8 dq1 3 dq5 dq12 dq4 v cc dq11 dq 3 dq0 oe# v ss ce# a0 v io rfu nc for gl256 s , gl12 8s nc for gl512 s , gl256 s , gl12 8s nc for gl12 8s
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 85 data sheet (preliminary) 11.1.2 physical diagram figure 11.2 56-pin thin small outline package (tsop), 14 x 20 mm notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
86 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 11.2 64-ball fbga 11.2.1 connection diagram figure 11.3 64-ball fortified ball grid array notes: 1. ball e1, do not use (dnu), a device internal signal is conne cted to the package connector. the connector may be used by spans ion for test or other purposes and is not intented for connection to any host system signal. do not use these connections for pcb signa l routing channels.. 2. balls f7 and g1, reserved for future use (rfu). 3. balls a1, a8, c1, d1, h1, and h8, no connect (nc). abcd efgh 8 nc a22 a2 3 vio v ss a2 4 a25 nc 7 a1 3 a12a14a15a16rfudq15v ss 6 a9 a 8 a10 a11 dq7 dq14 dq1 3 dq6 5 we# re s et# a21 a19 dq5 dq12 vcc dq4 4 ry/by# wp# a1 8 a20 dq2 dq10 dq11 dq 3 3 a7 a1 7 a6 a5 dq0 dq 8 dq9 dq1 2 a 3 a4 a2 a1 a0 ce# oe# v ss 1 nc dnu vio rfu nc top view product pino u t - nc for gl12 8s nc for gl512 s , gl256 s , gl12 8s nc for gl256 s , gl12 8s nc nc nc
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 87 data sheet (preliminary) 11.2.2 physical diagram figure 11.4 lae064?64-ball fortified ball grid array (fbga), 9 x 9 mm package lae 064 jedec n/a 9.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 9.00 bsc. body size e 9.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement ? none depopulated solder balls 3623 \ 16-038.12 \ 1.16.07 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010? except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in ? the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls.
88 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 11.2.3 special handling instru ctions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time.
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 89 data sheet (preliminary) 12. ordering information the ordering part number for the general market device is formed by a valid combination of the following: valid combinations the recommended combinations table lists configurat ions planned to be available in volume. the table below will be updated as new combinations are released. consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. notes: 1. package type 0 is standard option. 2. additional speed, package, and temperature options maybe offered in the future. check with your local sales representative fo r availability. s29gl01gs 10 d h i 01 0 packing type 0=tray 3 = 13? tape and reel model number (v io and v cc range) 01 = v io = v cc = 2.7 to 3.6v, highest address sector protected 02 = v io = v cc = 2.7 to 3.6v, lowest address sector protected v1 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, highest address sector protected v2 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, lowest address sector protected temperature range i = industrial (-40c to +85c) package materials set f = lead free (pb-free) h = low halogen, pb-free package type d = fortified ball-grid array package (lae064) 9 mm x 9 mm t = thin small outline package (tsop) standard pinout speed option 90 = 90 ns random access time 10 = 100 ns random access time 11 = 110 ns random access time 12 = 120 ns random access time device number/description s29gl01gs, s29gl512s, s29gl256s, s29gl128s 3.0 volt core, with v io option, 1024, 512, 256, 128 megabit page-mode flash memory, manufactured on 65 nm mirror bit eclipse process technology s29gl-s valid combinations base opn speed (ns) package and temperature model number packing type package description s29gl01gs 100, 110 tfi 01, 02 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm 110, 120 tfi v1, v2 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm s29gl512s 100, 110 tfi 01, 02 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm 110, 120 tfi v1, v2 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm s29gl256s 90, 100 tfi 01, 02 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm 100, 110 tfi v1, v2 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm s29gl128s 90, 100 tfi 01, 02 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm 100, 110 tfi v1, v2 0, 3 56-pin tsop dhi 64-ball fbga 9 mm x 9 mm
90 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 13. other resources visit www.spansion.com to obtain the following related documents: 13.1 links to software downloads and related information on flash device support is available at http://www.spansion.com/support/pages/driverssoftware.aspx ? spansion low-level drivers ? enhanced flash drivers ? flash file system downloads and related information on simulation modeling and cad modeling support is available at http://www.spansion.com/suppo rt/pages/simulationmodels.aspx ? vhdl and verilog ? ibis ? orcad 13.2 links to application notes the following is a list of application notes related to this product. all spansion application notes are available at http://www.spansion.com/support/technica ldocuments/pages/applicationnotes.aspx ? common flash interface version 1.5 vendor specific extensions ? common flash memory interface specification ? connecting unused data lines of mirrorbit flash ? developing system-level validation routines ? flash memory: an overview ? interfacing i.mx3x to s2 9gl mirrorbit nor flash ? interfacing the s29gl-s to freescale coldfire processor ? interfacing spansion gl mi rrorbit family to freescale i.mx31 processors ? mirrorbit flash memory write buffer programming and page buffer read ? optimizing program/erase times ? practical guide to endurance and data retention ? programmer?s guide for the spansion 65 nm gl-s eclipse family architecture ? reset voltage and timing requirements for mirrorbit flash ? signal integrity and reliable flash operations ? understanding ac characteristics ? understanding load capacitance and access time ? understanding page mode flash memory devices ? using cfi to read and debug systems ? versatile io: dq and enhanced ? wear leveling
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 91 data sheet (preliminary) 13.3 specification bulletins contact your local sales office for details. 13.4 contacting spansion obtain the latest list of company location s and contact information on our web site at http://www.spansion.com/about/pages/locations.aspx
92 gl-s mirrorbit ? family s29gl_128s_01gs_00_02 march 21, 2011 data sheet (preliminary) 14. revision history section description revision 01 (february 11, 2011) initial release revision 02 (march 21, 2011) global modified document from ?advance information? to ?preliminary? opn added fbga package offering for v1 & v2 model number removed kgd information, which is documented in a separate supplement command definitions table removed duplicated commands changed the number of command cycles for a cfi enter from 3 to 1 physical interface updated 56-pin tsop pinout figure updated 64-ball fbga pinout figure other resources added additional application notes in ?links to application notes? lock register table changed the default value of bit 7 in the lock register
march 21, 2011 s29gl_128s_01gs_00_02 gl-s mirrorbit ? family 93 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2011 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. ot her names used are for informational purposes only and ma y be trademarks of their respective owners.

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